Abstract: A semiconductor structure includes alternating stacks of insulating layers and electrically conductive layers which are located over a substrate and are laterally spaced apart among one another by first backside trenches and second backside trenches that are interlaced along a horizontal direction, first backside trench fill structures located in the first backside trenches, and second backside trench fill structures located in the second backside trenches. Each of the first backside trench fill structures includes a respective set of first backside bridge support structures comprising a first material, and each of the second backside trench fill structures includes a respective set of second backside bridge support structures comprising a second material that is different from the first material.

Abstract: A three-dimensional memory device includes at least one alternating stack of insulating layers and electrically conductive layers, memory openings vertically extending through the at least one alternating stack, memory opening fill structures located in the memory openings, and a laterally-extending trench fill structure contacting a first lengthwise sidewall of the at least one alternating stack, and including a first-type dielectric bridge structure having a first volume, a second-type dielectric bridge structure having a second volume greater than the first volume, and a trench dielectric material portion.

Abstract: A three-dimensional memory device includes a first alternating stack of first word lines and first insulating layers, first memory stack structures vertically extending through the first alternating stack, a second alternating stack of second word lines and second insulating layers, second memory stack structures vertically extending through the second alternating stack, plural backside trench fill structures located between the first alternating stack and the second alternating stack, and a bridge region located between the plural backside trench fill structures and between the between the first alternating stack and the second alternating stack. At least one insulating layer extends continuously through the first alternating stack, the second alternating stack, and the bridge region.

Abstract: A memory device includes layer stacks, each including a respective alternating stack of respective insulating layers and respective electrically conductive layers and a respective contact-level dielectric layer, memory openings vertically extending through a respective one of the alternating stacks. memory opening fill structures located in a respective one of the memory openings and including a respective vertical stack of memory elements and a respective vertical semiconductor channel, and dielectric bridges structures located within access trenches that laterally separate the layer stacks. Each of the dielectric bridge structures includes a respective pair of contoured sidewalls. Each contoured sidewall of the dielectric bridge structures includes at least two vertically-straight and horizontally-convex surface segments that are adjoined by a vertically-extending edge.

Abstract: A memory device includes a first alternating stack of first insulating layers and first electrically conductive layers, a first dielectric material portion overlying first stepped surfaces of the first alternating stack, a memory opening vertically extending through the first alternating stack, a memory opening fill structure located in the memory opening and including a vertical semiconductor channel and a vertical stack of memory elements, and a first contact via structure vertically extending through the first alternating stack and the first dielectric material portion. The first contact via structure includes a conductive pillar portion and a conductive fin portion that laterally protrudes from the conductive pillar portion and having a first annular bottom surface segment contacting an annular top surface segment of one of the first electrically conductive layers.

Abstract: A three-dimensional memory device includes laterally spaced apart vertical stacks of electrically conductive layers and insulating layers. A composite dielectric isolation structure provides electrical isolation between neighboring pairs of vertical stacks. The composite dielectric isolation structure includes at least one retro-stepped dielectric material portion, and may further include at least one finned insulating support structure or a vertical stack of dielectric material plates.

Abstract: Two types of support pillar structures are formed in a staircase region of an alternating stack of insulating layers and sacrificial material layers. First-type support pillar structures are formed in areas distal from backside trenches to be subsequently formed, and second-type support pillar structures may be formed in areas proximal to the backside trenches. The second-type support pillar structures may be formed as dielectric support pillar structures, or may be formed with at least one additional dielectric spacer.

Abstract: Technology is disclosed herein for preventing erase disturb in NAND. Erase voltages are applied to a source line and bit lines associated with selected memory cells, while applying an erase enable voltage to word lines connected to the selected cells. Preventing erase disturb may include raising the channel potential of unselected memory cells to a source line voltage that has a sufficiently low magnitude to not erase the unselected cells given a voltage on word lines connected to the unselected cells. The unselected cells share bit lines with the selected cells and may also share word lines. Preventing erase disturb may also include applying voltages to the select transistors that prevent the erase voltage from passing from the shared bit lines to the channels of the unselected cells. The voltages decrease from the bit lines to the unselected memory cells and may prevent GIDL generation. Current consumption is kept low.

Abstract: A memory device includes an alternating stack of insulating layers and electrically conductive layers, memory openings vertically extending through the alternating stack, memory opening fill structures located in the memory openings and including a respective memory film and a respective vertical semiconductor channel, contact wells vertically extending through a respective subset of layers of the alternating stack that includes a topmost insulating layer of the insulating layers, dielectric fill structures located in the contact wells, and an array of contact via structures vertically extending through the respective dielectric fill structure in each of the contact wells and contacting a top surface of a respective electrically conductive layer within a subset of the electrically conductive layers, the subset of the electrically conductive layers including a plurality of electrically conductive layers that are vertically spaced apart.

Abstract: A memory device includes a first-tier alternating stack of first insulating layers and electrically conductive layers located over a substrate, a second-tier alternating stack of second insulating layers and second electrically conductive layers overlying the first-tier alternating stack, a memory stack structure vertically extending through the first-tier alternating stack and the second-tier alternating stack, and a first support and contact assembly vertically extending through the first-tier alternating stack and the second-tier alternating stack. The first support and contact assembly includes a first contact via structure contacting an annular top surface of an electrically conductive layer, a first dielectric pillar structure underlying the reference-level electrically conductive layer, and a first-tier dielectric spacer that laterally surrounds the first contact via structure.

Abstract: A memory device includes at least one alternating stack of respective insulating layers and respective electrically conductive layers and memory stack structures vertically extending through the at least one alternating stack. A layer contact via structure contacts a top surface of one of the electrically conductive layers, and is laterally surrounded by at least one dielectric spacer, which may include a plurality of dielectric spacers, and optionally by a plurality of dielectric support pillar structures. Additionally or alternatively, the layer contact via structure may comprise a convex surface segment that is adjoined to a straight sidewall segment.

Abstract: A memory device includes at least one alternating stack of respective insulating layers and respective electrically conductive layers and memory stack structures vertically extending through the at least one alternating stack. A layer contact via structure contacts a top surface of one of the electrically conductive layers, and is laterally surrounded by at least one dielectric spacer, which may include a plurality of dielectric spacers, and optionally by a plurality of dielectric support pillar structures. Additionally or alternatively, the layer contact via structure may comprise a convex surface segment that is adjoined to a straight sidewall segment.

Abstract: Two types of support pillar structures are formed in a staircase region of an alternating stack of insulating layers and sacrificial material layers. First-type support pillar structures are formed in areas distal from backside trenches to be subsequently formed, and second-type support pillar structures may be formed in areas proximal to the backside trenches. The second-type support pillar structures may be formed as dielectric support pillar structures, or may be formed with at least one additional dielectric spacer.

Abstract: A semiconductor structure includes a vertical stack of repetition units, where each instance of the repetition unit extends along a first horizontal direction and includes a first electrically conductive strip, a first memory film located over the first electrically conductive strip, discrete semiconductor channels that are laterally spaced apart from each other along the first horizontal direction and located above the first memory film, a second memory film located above the discrete semiconductor channels, a second electrically conductive strip located above the second memory film, and an insulating strip located above the first electrically conductive strip.

Abstract: A semiconductor structure includes a vertical stack of repetition units, where each instance of the repetition unit extends along a first horizontal direction and includes a first electrically conductive strip, a first memory film located over the first electrically conductive strip, discrete semiconductor channels that are laterally spaced apart from each other along the first horizontal direction and located above the first memory film, a second memory film located above the discrete semiconductor channels, a second electrically conductive strip located above the second memory film, and an insulating strip located above the first electrically conductive strip.

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a plurality of source layers, where the electrically conductive layers include word lines and source-side select gate electrodes which are located between the plurality of source layers and the word lines in a vertical direction, groups of memory openings vertically extending through the alternating stack, and groups of memory opening fill structures located in the groups of memory openings. The plurality of source layers are laterally spaced apart and electrically isolated from each other, and each respective one of the plurality of source layers contacts at least one respective group of the groups of memory opening fill structures.

Abstract: A memory device includes a semiconductor channel, a gate electrode, and a stack located between the semiconductor channel and the gate electrode. The stack includes, from one side to another, a first ferroelectric material portion, a second ferroelectric material portion, and a gate dielectric portion that contacts the semiconductor channel.

Abstract: A memory device includes a first memory block containing first word lines and a first source layer segment, and a second memory block containing second word lines and a second source layer segment which is electrically isolated from the first source layer segment. The first word lines in the first memory block are electrically connected to the respective second word lines in the second memory block.

Abstract: Technology is disclosed herein for preventing erase disturb in NAND. Erase voltages are applied to a source line and bit lines associated with selected memory cells, while applying an erase enable voltage to word lines connected to the selected cells. Preventing erase disturb may include raising the channel potential of unselected memory cells to a source line voltage that has a sufficiently low magnitude to not erase the unselected cells given a voltage on word lines connected to the unselected cells. The unselected cells share bit lines with the selected cells and may also share word lines. Preventing erase disturb may also include applying voltages to the select transistors that prevent the erase voltage from passing from the shared bit lines to the channels of the unselected cells. The voltages decrease from the bit lines to the unselected memory cells and may prevent GIDL generation. Current consumption is kept low.

Abstract: A three-dimensional memory device includes alternating stacks of insulating layers and electrically conductive layers that laterally extending along a first horizontal direction, and laterally spaced apart along a second horizontal direction by lateral isolation trenches, memory stack structures vertically extending through a respective one of the alternating stacks; and isolation trench fill structures located in the lateral isolation trenches. At least one of the isolation trench fill structures includes a first lengthwise sidewall and a second lengthwise sidewall. The first lengthwise sidewall has a first periodic lateral undulation with a uniform pitch along the first horizontal direction. The second lengthwise sidewall has a second periodic lateral undulation with the uniform pitch along the first horizontal direction.