Patents by Inventor Johann Alsmeier

Johann Alsmeier has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210005617
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and an array of memory opening fill structures extending through the alternating stack, an array of drain-select-level assemblies overlying the alternating stack and having a same two-dimensional periodicity as the array of memory opening fill structures, a first strip electrode portion laterally surrounding a first set of multiple rows of drain-select-level assemblies within the array of drain-select-level assemblies, and a drain-select-level isolation strip including an isolation dielectric that contacts the first strip electrode portion and laterally spaced from the drain-select-level assemblies and extending between the first strip electrode portion and a second strip electrode portion.
    Type: Application
    Filed: September 24, 2020
    Publication date: January 7, 2021
    Inventors: James KAI, Murshed CHOWDHURY, Masaaki HIGASHITANI, Johann ALSMEIER
  • Publication number: 20200411072
    Abstract: A ferroelectric memory unit cell includes a series connection of select gate transistor that turns the ferroelectric memory unit cell on and off, and a ferroelectric memory transistor. Data is stored in a ferroelectric material layer of the ferroelectric memory transistor. The ferroelectric memory unit cell may be a planar structure in which both transistors are planar transistors with horizontal current directions. In this case, the gate electrode of the access transistor can be formed as a buried conductive line. Alternatively, the ferroelectric memory unit cell may include a vertical stack of vertical semiconductor channels.
    Type: Application
    Filed: June 27, 2019
    Publication date: December 31, 2020
    Inventors: Yanli ZHANG, Johann ALSMEIER
  • Publication number: 20200411554
    Abstract: A memory device includes a semiconductor channel extending between a source region and a drain region, a plurality of pass gate electrodes, a plurality of word lines, a gate dielectric located between the semiconductor channel and the plurality of pass gate electrodes, and ferroelectric material portions located between the semiconductor channel and the plurality of word lines.
    Type: Application
    Filed: June 28, 2019
    Publication date: December 31, 2020
    Inventors: Yanli Zhang, Johann Alsmeier
  • Publication number: 20200411553
    Abstract: A ferroelectric memory unit cell includes a series connection of select gate transistor that turns the ferroelectric memory unit cell on and off, and a ferroelectric memory transistor. Data is stored in a ferroelectric material layer of the ferroelectric memory transistor. The ferroelectric memory unit cell may be a planar structure in which both transistors are planar transistors with horizontal current directions. In this case, the gate electrode of the access transistor can be formed as a buried conductive line. Alternatively, the ferroelectric memory unit cell may include a vertical stack of vertical semiconductor channels.
    Type: Application
    Filed: June 27, 2019
    Publication date: December 31, 2020
    Inventors: Yanli ZHANG, Johann ALSMEIER
  • Publication number: 20200411533
    Abstract: A memory cell includes a ferroelectric memory transistor, and a select gate transistor which shares a common semiconductor channel, a common source region and a common drain region with the ferroelectric memory transistor. The select gate transistor controls access between the common source region and the common semiconductor channel.
    Type: Application
    Filed: June 28, 2019
    Publication date: December 31, 2020
    Inventors: Johann ALSMEIER, Yanli ZHANG
  • Patent number: 10879269
    Abstract: A ferroelectric memory unit cell includes a series connection of select gate transistor that turns the ferroelectric memory unit cell on and off, and a ferroelectric memory transistor. Data is stored in a ferroelectric material layer of the ferroelectric memory transistor. The ferroelectric memory unit cell may be a planar structure in which both transistors are planar transistors with horizontal current directions. In this case, the gate electrode of the access transistor can be formed as a buried conductive line. Alternatively, the ferroelectric memory unit cell may include a vertical stack of vertical semiconductor channels.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: December 29, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yanli Zhang, Johann Alsmeier
  • Patent number: 10868042
    Abstract: A memory device includes a semiconductor channel extending between a source region and a drain region, a plurality of pass gate electrodes, a plurality of word lines, a gate dielectric located between the semiconductor channel and the plurality of pass gate electrodes, and ferroelectric material portions located between the semiconductor channel and the plurality of word lines.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: December 15, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yanli Zhang, Johann Alsmeier
  • Publication number: 20200365618
    Abstract: A memory device includes a semiconductor channel, a gate electrode, and a stack located between the semiconductor channel and the gate electrode. The stack includes, from one side to another, a first ferroelectric material portion, a second ferroelectric material portion, and a gate dielectric portion that contacts the semiconductor channel.
    Type: Application
    Filed: May 15, 2019
    Publication date: November 19, 2020
    Inventors: Yanli ZHANG, Johann ALSMEIER
  • Patent number: 10840260
    Abstract: An alternating stack of insulating layers and dielectric spacer layers is formed over a semiconductor substrate. Memory stack structures are formed through the alternating stack. Backside trenches, a moat trench, and a contact opening are formed through the alternating stack, and are subsequently filled with sacrificial backside trench fill material structures, a sacrificial moat trench fill structure, and a sacrificial contact opening fill structure, respectively. The sacrificial moat trench fill structure is replaced with tubular dielectric wall structure. Portions of the dielectric spacer layers located outside the tubular dielectric wall structure are replaced with electrically conductive layers. The sacrificial backside trench fill material structures are replaced with backside trench fill structures. The sacrificial contact opening fill structure is replaced with a conductive via structure.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: November 17, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: James Kai, Murshed Chowdhury, Fumiaki Toyama, Johann Alsmeier, Masaaki Higashitani
  • Publication number: 20200357783
    Abstract: A first wafer including a first substrate, first semiconductor devices overlying the first substrate, and first dielectric material layers overlying the first semiconductor devices is provided. A sacrificial material layer is formed over a top surface of a second wafer including a second substrate. Second semiconductor devices and second dielectric material layers are formed over a top surface of the sacrificial material layer. The second wafer is attached to the first wafer such that the second dielectric material layers face the first dielectric material layers. A plurality of voids is formed through the second substrate. The sacrificial material layer is removed by providing an etchant that etches a material of the sacrificial material layer through the plurality of voids. The substrate is detached from a bonded assembly including the first wafer, the second semiconductor devices, and the second dielectric material layers upon removal of the sacrificial material layer.
    Type: Application
    Filed: June 12, 2020
    Publication date: November 12, 2020
    Inventors: James Kai, Murshed Chowdhury, Koichi Matsuno, Johann Alsmeier
  • Patent number: 10825826
    Abstract: Three-dimensional memory devices in the form of a memory die includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and memory stack structures extending through the alternating stack, in which each of the memory stack structures includes a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film. Bit lines are electrically connected to an end portion of a respective one of the vertical semiconductor channels. Bump connection via structures contact a top surface of a respective one of the bit lines, in which each of the bump connection via structures has a greater lateral dimension along a lengthwise direction of the bit lines than along a widthwise direction of the bit lines. Metallic bump structures of another semiconductor die contact respective ones of the bump connection via structures to make respective electrical connections between the two dies.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: November 3, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Jixin Yu, Tae-Kyung Kim, Johann Alsmeier, Yan Li, Jian Chen
  • Publication number: 20200343235
    Abstract: A memory device includes a memory die containing memory elements, a support die containing peripheral devices and bonded to the memory die, and an electrically conductive path between two of the peripheral devices which extends at least partially through the memory die. The electrically conductive path is electrically isolated from the memory elements.
    Type: Application
    Filed: June 12, 2020
    Publication date: October 29, 2020
    Inventors: Yanli Zhang, Kwang-Ho Kim, Johann Alsmeier
  • Patent number: 10811058
    Abstract: A bonded assembly includes a memory die bonded to a support die. The memory die contains at least one three-dimensional array of memory elements, memory-die dielectric material layers, and memory-die bonding pads. The support die contains at least one peripheral circuitry including complementary metal-oxide-semiconductor (CMOS) devices and configured to generate control signals for, and receive sense signals from, the at least one three-dimensional array of memory elements and a functional module and configured to provide a functionality that is independent of operation of the at least one three-dimensional array of memory elements. The functional module may include an error correction code (ECC) module, a memory module configured to interface with an external processor module located outside of the memory die, a microprocessor unit module, a wireless communication module, and/or a system level controller module.
    Type: Grant
    Filed: February 6, 2019
    Date of Patent: October 20, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yanli Zhang, Zhixin Cui, Akio Nishida, Johann Alsmeier, Yan Li, Steven Sprouse
  • Publication number: 20200295029
    Abstract: Three-dimensional memory devices in the form of a memory die includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and memory stack structures extending through the alternating stack, in which each of the memory stack structures includes a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film. Bit lines are electrically connected to an end portion of a respective one of the vertical semiconductor channels. Bump connection via structures contact a top surface of a respective one of the bit lines, in which each of the bump connection via structures has a greater lateral dimension along a lengthwise direction of the bit lines than along a widthwise direction of the bit lines. Metallic bump structures of another semiconductor die contact respective ones of the bump connection via structures to make respective electrical connections between the two dies.
    Type: Application
    Filed: June 1, 2020
    Publication date: September 17, 2020
    Inventors: Jixin Yu, Tae-Kyung Kim, Johann Alsmeier, Yan Li, Jian Chen
  • Publication number: 20200295030
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through the alternating stack, and memory stack structures located within a respective one of the memory openings. A multi-pillared dielectric isolation structure extends through upper sections of a neighboring pair of memory openings. The multi-pillared dielectric isolation structure includes a plurality of dielectric pillar portions located within a respective one of the memory openings, and at least one horizontally-extending portion adjoining each of the plurality of dielectric pillar portions and located between a vertically neighboring pair of insulating layers within the alternating stack. The at least one horizontally-extending portion laterally separates laterally neighboring strips of at least one electrically conductive layer within the alternating stack.
    Type: Application
    Filed: March 13, 2019
    Publication date: September 17, 2020
    Inventors: Tae-Kyung KIM, Johann ALSMEIER
  • Publication number: 20200286905
    Abstract: A memory die including a three-dimensional array of memory elements and a logic die including a peripheral circuitry that support operation of the three-dimensional array of memory elements can be bonded by die-to-die bonding to provide a bonded assembly. External bonding pads for the bonded assembly can be provided by forming recess regions through the memory die or through the logic die to physically expose metal interconnect structures within interconnect-level dielectric layers. The external bonding pads can include, or can be formed upon, a physically exposed subset of the metal interconnect structures. Alternatively or additionally, laterally-insulated external connection via structures can be formed through the bonded assembly to multiple levels of the metal interconnect structures. Further, through-dielectric external connection via structures extending through a stepped dielectric material portion of the memory die can be physically exposed, and external bonding pads can be formed thereupon.
    Type: Application
    Filed: March 4, 2019
    Publication date: September 10, 2020
    Inventors: James KAI, Murshed CHOWDHURY, Koichi MATSUNO, Johann ALSMEIER
  • Patent number: 10748894
    Abstract: A memory die includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures extending through the alternating stack, source regions located on, or in, the substrate, and at least one memory-side bonding pad electrically connected to the source regions. A logic die includes a power supply circuit configured to generate a supply voltage for the source regions, and at least one logic-side bonding pad electrically connected to the power supply circuit through a network of logic-side metal interconnect structures. The memory die is bonded to the logic die. The network of logic-side metal interconnect structures distributes source power from the power supply circuit over an entire area of the memory stack structures and transmits the source power to the memory die through bonded pairs of memory-side bonding pads and logic-side bonding pads.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: August 18, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Murshed Chowdhury, Kwang-Ho Kim, James Kai, Johann Alsmeier
  • Publication number: 20200258904
    Abstract: A three-dimensional memory device may include an alternating stack of insulating layers and spacer material layers formed over a carrier substrate. The spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers. Memory stack structures are formed through the alternating stack. Each memory stack structure includes a respective vertical semiconductor channel and a respective memory film. Drain regions and bit lines can be formed over the memory stack structures to provide a memory die. The memory die can be bonded to a logic die containing peripheral circuitry for supporting operations of memory cells within the memory die. A distal end of each of the vertical semiconductor channels is physically exposed by removing the carrier substrate. A source layer is formed directly on the distal end each of the vertical semiconductor channels. A bonding pad can be formed on the source layer.
    Type: Application
    Filed: March 12, 2020
    Publication date: August 13, 2020
    Inventors: James KAI, Ching-Huang LU, Murshed CHOWDHURY, Johann ALSMEIER
  • Publication number: 20200251149
    Abstract: A bonded assembly includes a memory die bonded to a support die. The memory die contains at least one three-dimensional array of memory elements, memory-die dielectric material layers, and memory-die bonding pads. The support die contains at least one peripheral circuitry including complementary metal-oxide-semiconductor (CMOS) devices and configured to generate control signals for, and receive sense signals from, the at least one three-dimensional array of memory elements and a functional module and configured to provide a functionality that is independent of operation of the at least one three-dimensional array of memory elements. The functional module may include an error correction code (ECC) module, a memory module configured to interface with an external processor module located outside of the memory die, a microprocessor unit module, a wireless communication module, and/or a system level controller module.
    Type: Application
    Filed: February 6, 2019
    Publication date: August 6, 2020
    Inventors: Yanli ZHANG, Zhixin CUI, Akio NISHIDA, Johann ALSMEIER, Yan LI, Steven SPROUSE
  • Publication number: 20200243498
    Abstract: A memory device includes a memory die containing memory elements, a support die containing peripheral devices and bonded to the memory die, and an electrically conductive path between two of the peripheral devices which extends at least partially through the memory die. The electrically conductive path is electrically isolated from the memory elements.
    Type: Application
    Filed: January 30, 2019
    Publication date: July 30, 2020
    Inventors: Yanli ZHANG, Kwang-Ho KIM, Johann ALSMEIER