Patents by Inventor Johann Alsmeier

Johann Alsmeier has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220181348
    Abstract: A three-dimensional memory device includes layer stacks located over a substrate and laterally spaced apart from each other by backside trenches. Each of the layer stacks includes a respective alternating stack of insulating layers and electrically conductive layers. Memory openings vertically extend through a respective one of the alternating stacks and are filled with a respective memory opening fill structure. Each of the memory opening fill structures includes a respective vertical semiconductor channel and a respective vertical stack of memory elements. Each backside trench fill structure includes a respective row of backside trench bridge structures that are more distal from the substrate than a most distal one of the electrically conductive layers is from the substrate. The backside trench bridge structures can provide structural support during a replacement process that forms the electrically conductive layers.
    Type: Application
    Filed: December 9, 2020
    Publication date: June 9, 2022
    Inventors: Koichi MATSUNO, Jixin YU, Johann ALSMEIER
  • Patent number: 11296101
    Abstract: A three-dimensional memory device includes a first-tier alternating stack of first insulating layers and first electrically conductive layers located over a substrate, an etch stop material layer located over the first-tier alternating stack, a second-tier alternating stack of second insulating layers and second electrically conductive layers located over the etch stop material layer, inter-tier memory openings vertically extending through the second-tier alternating stack, the etch stop material layer, and the first-tier alternating stack, and memory opening fill structures each including a memory film and a vertical semiconductor channel located in the inter-tier memory openings. The material of the etch stop material layer is different from materials of the first insulating layers, the second insulating layers, the first electrically conductive layers, and the second electrically conductive layers.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: April 5, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yao-Sheng Lee, Senaka Kanakamedala, Raghuveer S. Makala, Johann Alsmeier
  • Patent number: 11251199
    Abstract: A semiconductor structure includes vertically-alternating stacks of insulating strips and electrically conductive strips located over a substrate and laterally spaced apart from each other by line trenches. Laterally-alternating sequences of semiconductor region assemblies and dielectric pillar structures are located within a respective one of the line trenches. Memory films are located between each neighboring pair of the vertically-alternating stacks and the laterally-alternating sequences. Each of the semiconductor region assemblies includes a source pillar structure, a drain pillar structure, and a channel structure including a pair of lateral semiconductor channels that laterally connect the source pillar structure and the drain pillar structure. The memory films may include a charge storage layer or a ferroelectric material layer.
    Type: Grant
    Filed: December 9, 2019
    Date of Patent: February 15, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yanli Zhang, Johann Alsmeier
  • Publication number: 20220028846
    Abstract: A bonded assembly includes a first three-dimensional memory die containing a first alternating stack of first insulating layers and first electrically conductive layers and first memory structures located in the first alternating stack, a second three-dimensional memory die bonded to the first three-dimensional memory die, and containing a second alternating stack of second insulating layers and second electrically conductive layers, and second memory structures located in the second alternating stack. The first electrically conductive layers have different lateral extents along the first horizontal direction that decrease with a respective vertical distance from driver circuit devices, and the second electrically conductive layers have different lateral extents along the first horizontal direction that increase with the respective vertical distance from the driver circuit devices.
    Type: Application
    Filed: July 22, 2020
    Publication date: January 27, 2022
    Inventors: Johann ALSMEIER, James KAI, Koichi MATSUNO
  • Patent number: 11222881
    Abstract: A memory device includes a memory die containing memory elements, a support die containing peripheral devices and bonded to the memory die, and an electrically conductive path between two of the peripheral devices which extends at least partially through the memory die. The electrically conductive path is electrically isolated from the memory elements.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: January 11, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yanli Zhang, Kwang-Ho Kim, Johann Alsmeier
  • Publication number: 20210408019
    Abstract: At least a portion of a memory cell is formed over a first substrate and at least a portion of a steering element or word or bit line of the memory cell is formed over a second substrate. The at least a portion of the memory cell is bonded to at least a portion of a steering element or word or bit line. At least one of the first or second substrate may be removed after the bonding.
    Type: Application
    Filed: June 26, 2020
    Publication date: December 30, 2021
    Inventors: Raghuveer S. MAKALA, Johann ALSMEIER
  • Publication number: 20210408020
    Abstract: At least a portion of a memory cell is formed over a first substrate and at least a portion of a steering element or word or bit line of the memory cell is formed over a second substrate. The at least a portion of the memory cell is bonded to at least a portion of a steering element or word or bit line. At least one of the first or second substrate may be removed after the bonding.
    Type: Application
    Filed: June 26, 2020
    Publication date: December 30, 2021
    Inventors: Raghuveer S. MAKALA, Johann ALSMEIER
  • Patent number: 11195857
    Abstract: A three-dimensional memory device may include an alternating stack of insulating layers and spacer material layers formed over a carrier substrate. The spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers. Memory stack structures are formed through the alternating stack. Each memory stack structure includes a respective vertical semiconductor channel and a respective memory film. Drain regions and bit lines can be formed over the memory stack structures to provide a memory die. The memory die can be bonded to a logic die containing peripheral circuitry for supporting operations of memory cells within the memory die. A distal end of each of the vertical semiconductor channels is physically exposed by removing the carrier substrate. A source layer is formed directly on the distal end each of the vertical semiconductor channels. A bonding pad can be formed on the source layer.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: December 7, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: James Kai, Ching-Huang Lu, Murshed Chowdhury, Johann Alsmeier
  • Publication number: 20210358946
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through the alternating stack, memory opening fill structures located within a respective one of the memory openings, and at least one drain-select-level isolation structure vertically extending through at least a topmost electrically conductive layer among the electrically conductive layers. The at least one drain-select-level isolation structure may include wiggles and cut through upper portions of at least some of the memory opening fill structures, or may include a vertically-extending dielectric material portion and laterally-protruding dielectric material portions adjoined to the vertically-extending dielectric material portion and laterally protruding into lateral recesses located adjacent to the at least the topmost electrically conductive layer.
    Type: Application
    Filed: July 26, 2021
    Publication date: November 18, 2021
    Inventors: Srinivas PULUGURTHA, Johann ALSMEIER, Yanli ZHANG, James KAI
  • Patent number: 11164890
    Abstract: A semiconductor structure includes layer stack structures laterally extending along a first horizontal direction and spaced apart from each other along a second horizontal direction by line trenches. Each of the layer stack structures includes at least one instance of a unit layer sequence that includes, from bottom to top or top to bottom, a doped semiconductor source strip, a channel-level insulating strip, and a doped semiconductor drain strip. Line trench fill structures are located within a respective one of the line trenches. Each of the line trench fill structures includes a laterally-alternating sequence of memory pillar structures and dielectric pillar structures. Each of the memory pillar structures includes a gate electrode, at least one pair of ferroelectric dielectric layers, and at least one pair of vertical semiconductor channels located at each level of the channel-level insulating strips.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: November 2, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yanli Zhang, Johann Alsmeier, Fei Zhou
  • Publication number: 20210335805
    Abstract: A three-dimensional memory device includes an alternating stack of word lines and at least one insulating layers or air gaps located over a substrate, a memory opening fill structure extending through the alternating stack. The memory opening fill structure includes a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film. The word lines are thicker than the insulating layers or air gaps.
    Type: Application
    Filed: April 27, 2020
    Publication date: October 28, 2021
    Inventors: James KAI, Senaka KANAKAMEDALA, Johann ALSMEIER
  • Publication number: 20210335999
    Abstract: A three-dimensional memory device includes an alternating stack of word lines and at least one insulating layers or air gaps located over a substrate, a memory opening fill structure extending through the alternating stack. The memory opening fill structure includes a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film. The word lines are thicker than the insulating layers or air gaps.
    Type: Application
    Filed: April 27, 2020
    Publication date: October 28, 2021
    Inventors: James KAI, Senaka KANAKAMEDALA, Johann ALSMEIER
  • Patent number: 11139272
    Abstract: A method of forming a bonded assembly includes providing a first semiconductor die containing a first substrate, first semiconductor devices, and first bonding pads that are electrically connected to a respective node of the first semiconductor devices, forming a first oxidation barrier layer on physically exposed surfaces of the first bonding pads, providing a second semiconductor die containing a second substrate, second semiconductor devices, and second bonding pads that are electrically connected to a respective node of the second semiconductor devices, and bonding the second bonding pads to the first bonding pads with at least the first oxidation barrier layer located between the respective first and second bonding pads.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: October 5, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Raghuveer S. Makala, Johann Alsmeier
  • Publication number: 20210305266
    Abstract: A three-dimensional memory device includes a first-tier alternating stack of first insulating layers and first electrically conductive layers located over a substrate, an etch stop material layer located over the first-tier alternating stack, a second-tier alternating stack of second insulating layers and second electrically conductive layers located over the etch stop material layer, inter-tier memory openings vertically extending through the second-tier alternating stack, the etch stop material layer, and the first-tier alternating stack, and memory opening fill structures each including a memory film and a vertical semiconductor channel located in the inter-tier memory openings. The material of the etch stop material layer is different from materials of the first insulating layers, the second insulating layers, the first electrically conductive layers, and the second electrically conductive layers.
    Type: Application
    Filed: March 27, 2020
    Publication date: September 30, 2021
    Inventors: Yao-Sheng Lee, Senaka KANAKAMEDALA, Raghuveer S. Makala, Johann ALSMEIER
  • Patent number: 11127729
    Abstract: A first wafer including a first substrate, first semiconductor devices overlying the first substrate, and first dielectric material layers overlying the first semiconductor devices is provided. A sacrificial material layer is formed over a top surface of a second wafer including a second substrate. Second semiconductor devices and second dielectric material layers are formed over a top surface of the sacrificial material layer. The second wafer is attached to the first wafer such that the second dielectric material layers face the first dielectric material layers. A plurality of voids is formed through the second substrate. The sacrificial material layer is removed by providing an etchant that etches a material of the sacrificial material layer through the plurality of voids. The substrate is detached from a bonded assembly including the first wafer, the second semiconductor devices, and the second dielectric material layers upon removal of the sacrificial material layer.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: September 21, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: James Kai, Murshed Chowdhury, Koichi Matsuno, Johann Alsmeier
  • Patent number: 11094704
    Abstract: A method of forming a device structure includes forming a memory-level structure including a three-dimensional memory device over a front side surface of a semiconductor substrate, forming memory-side dielectric material layers over the memory-level structure, bonding a handle substrate to the memory-side dielectric material layers, thinning the semiconductor substrate while the handle substrate is attached to the memory-side dielectric material layers, forming a driver circuit including field effect transistors on a backside semiconductor surface of the semiconductor substrate after thinning the semiconductor substrate, and removing the handle substrate from the memory-side dielectric material layers.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: August 17, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yanli Zhang, Johann Alsmeier, Teruo Okina
  • Patent number: 11088170
    Abstract: A ferroelectric field effect transistor (FeFET) includes a semiconductor channel, a source region contacting one end of the semiconductor channel, a drain region contacting a second end of the semiconductor channel, a gate electrode, a ferroelectric gate dielectric layer located between the semiconductor channel and the gate electrode, and a bidirectional selector material layer located between the gate electrode and the ferroelectric gate dielectric layer.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: August 10, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Yanli Zhang, Johann Alsmeier
  • Publication number: 20210217775
    Abstract: A semiconductor structure includes layer stack structures laterally extending along a first horizontal direction and spaced apart from each other along a second horizontal direction by line trenches. Each of the layer stack structures includes at least one instance of a unit layer sequence that includes, from bottom to top or top to bottom, a doped semiconductor source strip, a channel-level insulating strip, and a doped semiconductor drain strip. Line trench fill structures are located within a respective one of the line trenches. Each of the line trench fill structures includes a laterally-alternating sequence of memory pillar structures and dielectric pillar structures. Each of the memory pillar structures includes a gate electrode, at least one pair of ferroelectric dielectric layers, and at least one pair of vertical semiconductor channels located at each level of the channel-level insulating strips.
    Type: Application
    Filed: January 9, 2020
    Publication date: July 15, 2021
    Inventors: Yanli ZHANG, Johann ALSMEIER, Fei ZHOU
  • Publication number: 20210210503
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory stack structures vertically extending through the alternating stack, wherein each of the memory stack structures comprises a vertical semiconductor channel and a vertical stack of memory elements, a dielectric moat structure vertically extending through the alternating stack and including an annular dielectric plate portion at each level of the electrically conductive layers that laterally surrounds a respective dielectric material plate, and an interconnection via structure laterally surrounded by the dielectric moat structure and vertically extending through each insulating layer within the alternating stack.
    Type: Application
    Filed: November 30, 2020
    Publication date: July 8, 2021
    Inventors: Koichi MATSUNO, James KAI, Jixin YU, Johann ALSMEIER, Yoshitaka OTSU
  • Patent number: 11043455
    Abstract: A vertically alternating sequence of continuous insulating layers and continuous sacrificial material layers is formed over a substrate. Memory stack structures are formed through the vertically alternating sequence. The vertically alternating sequence is divided into alternating stacks of insulating layers and sacrificial material layers by forming backside trenches therethrough. Each neighboring pair of alternating stacks is laterally spaced apart from each other by a respective backside trench. The sacrificial material layers are replaced with multipart layers.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: June 22, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: James Kai, Johann Alsmeier, Jixin Yu