Abstract: A filter that has a resonator operated in series resonance and a two-pole terminal resonator circuit with a resonator whose electric conductance can be divided into a useful component and a parasitic component. A first differential stage actuated by a signal source and having two active elements whose ground connections are each linked to a respective current source and to a respective connection of the two-terminal resonator. A compensation circuit having two connections and which simulates the parasitic component of the resonator electric conductance is connected to a second differential stage which actuated by the signal source, is of the same type as the first differential stage, and has two active elements whose ground connections are each linked to a respective current source and to a respective connection of the compensation circuit. An evaluation circuit is linked to the two mutually reversed, i.e. connected in phase opposition, output connections of the two differential stages.

Abstract: A receiver array in accordance with the reception principle of synchronous demodulation, in which a controllable oscillator array is pre-synchronized to a set value for the oscillator frequency by a digital first control circuit having a reference frequency source during a pre-synchronization phase, and a heterodyne signal derived from the oscillator frequency is then synchronized with phase locking to the received useful signal by switching the oscillator control input to an analog second control circuit.

Abstract: In a switching network in matrix form for megahertz frequency signals, including: a multilayer printed circuit board having a plurality of row signal lines located in a first plane, a plurality of column signal lines located in a second plane and extending transverse to the row lines, the row and column signal lines intersecting one another in an intersection area, control and/or shielding conductors surrounding the lines, and metal shields enclosing the planes; a crosspoint array integrated on a chip and providing a plurality of crosspoints for the intersection area, each crosspoint presenting two semiconductor switches arranged to couple a respective column signal line to a respective row signal line; and a shielded package enclosing the chip, each line is constituted by a balanced pair of stripline conductors and is terminated at each end by its characteristic impedance.