Patents by Inventor Johann C. Rode
Johann C. Rode has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11881511Abstract: A transistor is disclosed. The transistor includes a substrate, a superlattice structure that includes a plurality of heterojunction channels, and a gate that extends to one of the plurality of heterojunction channels. The transistor also includes a source adjacent a first side of the superlattice structure and a drain adjacent a second side of the superlattice structure.Type: GrantFiled: December 19, 2018Date of Patent: January 23, 2024Assignee: Intel CorporationInventors: Nidhi Nidhi, Rahul Ramaswamy, Sansaptak Dasgupta, Han Wui Then, Marko Radosavljevic, Johann C. Rode, Paul B. Fischer, Walid M. Hafez
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Patent number: 11757027Abstract: Embodiments include a transistor and methods of forming such transistors. In an embodiment, the transistor comprises a semiconductor substrate, a barrier layer over the semiconductor substrate; a polarization layer over the barrier layer, an insulating layer over the polarization layer, a gate electrode through the insulating layer and the polarization layer, a spacer along sidewalls of the gate electrode, and a gate dielectric between the gate electrode and the barrier layer.Type: GrantFiled: December 13, 2018Date of Patent: September 12, 2023Assignee: Intel CorporationInventors: Rahul Ramaswamy, Nidhi Nidhi, Walid M. Hafez, Johann C. Rode, Paul Fischer, Han Wui Then, Marko Radosavljevic, Sansaptak Dasgupta
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Patent number: 11688788Abstract: An integrated circuit includes a gate structure in contact with a portion of semiconductor material between a source region and a drain region. The gate structure includes gate dielectric and a gate electrode. The gate dielectric includes at least two hybrid stacks of dielectric material. Each hybrid stack includes a layer of low-? dielectric and a layer of high-? dielectric on the layer of low-? dielectric, where the layer of high-? dielectric has a thickness at least two times the thickness of the layer of low-? dielectric. In some cases, the layer of low-? dielectric has a thickness no greater than 1.5 nm. The layer of high-? dielectric may be a composite layer that includes two or more layers of compositionally-distinct materials. The gate structure can be used with any number of transistor configurations but is particularly useful with respect to group III-V transistors.Type: GrantFiled: December 4, 2018Date of Patent: June 27, 2023Assignee: Intel CorporationInventors: Johann C. Rode, Samuel J. Beach, Nidhi Nidhi, Rahul Ramaswamy, Han Wui Then, Walid Hafez
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Publication number: 20230197840Abstract: In one embodiment, a transistor includes a substrate, a buffer layer on the substrate a channel layer on the buffer layer, and one or more polarization layers on the channel layer. The one or more polarization layers include a group III-N material comprising a first group III constituent and a second group III constituent. The transistor further includes a plurality of p-type doped layers on the one or more polarization layers. Each of the plurality of p-type doped layers includes a first p-type dopant and the III-N material, wherein each successive layer of the first p-type doped layers has a lower proportion of the first group III constituent to the second group III constituent relative to a layer below it. The transistor also includes a p-type doped layer on the plurality of p-type doped layers comprising a second p-type dopant and a group III-N material.Type: ApplicationFiled: December 21, 2021Publication date: June 22, 2023Applicant: Intel CorporationInventors: Sanyam Bajaj, Michael S. Beumer, Robert Ehlert, Gregory P. McNerney, Nicholas Minutillo, Xiaoye Qin, Johann C. Rode, Atsunori Tanaka, Suresh Vishwanath, Patrick M. Wallace
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Publication number: 20230132548Abstract: In one embodiment, a transistor is formed by a process comprising forming a buffer layer on a substrate, the buffer layer comprising a first group III-nitride (III-N) material (e.g., AlGaN), forming a channel layer on the buffer layer, the channel layer comprising a second III-N material (e.g., GaN), forming a polarization layer on the channel layer, the polarization layer comprising a third III-N material (e.g., AlGaN), flowing a p-type dopant precursor compound (e.g., Cp2Mg) after forming the polarization layer, forming a p-type doped layer (e.g., p-GaN) on the polarization layer, the p-type doped layer comprising a p-type dopant (e.g., Mg) and a fourth III-N material (e.g., GaN), forming a source region adjacent one end of the channel layer, and forming a drain region adjacent another end of the channel layer.Type: ApplicationFiled: November 4, 2021Publication date: May 4, 2023Applicant: Intel CorporationInventors: Atsunori Tanaka, Sanyam Bajaj, Michael S. Beumer, Robert Ehlert, Gregory P. McNerney, Nicholas Minutillo, Johann C. Rode, Suresh Vishwanath, Patrick M. Wallace
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Patent number: 11626513Abstract: Embodiments include a transistor and methods of forming a transistor. In an embodiment, the transistor comprises a semiconductor channel, a source electrode on a first side of the semiconductor channel, a drain electrode on a second side of the semiconductor channel, a polarization layer over the semiconductor channel, an insulator stack over the polarization layer, and a gate electrode over the semiconductor channel. In an embodiment, the gate electrode comprises a main body that passes through the insulator stack and the polarization layer, and a first field plate extending out laterally from the main body.Type: GrantFiled: December 13, 2018Date of Patent: April 11, 2023Assignee: Intel CorporationInventors: Rahul Ramaswamy, Nidhi Nidhi, Walid M. Hafez, Johann C. Rode, Paul Fischer, Han Wui Then, Marko Radosavljevic, Sansaptak Dasgupta, Heli Chetanbhai Vora
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Publication number: 20200219772Abstract: An integrated circuit structure and methodologies of forming same. In an embodiment, the integrated circuit structure includes a transistor gate structure in a first region of semiconductor material and a diode in a second region of the semiconductor material. The gate structure has a gate electrode of conductive material with a liner along sides and a bottom of the gate electrode. The gate electrode has a gate length less than a threshold dimension value. The diode includes a body of the conductive material in contact with the semiconductor material and includes the liner along sides of the body of conductive material. The body of conductive material has a lateral dimension greater than the threshold dimension value. The liner can include, for example, a gate dielectric and a diffusion barrier in some embodiments. In other embodiments, the liner is the gate dielectric (without any diffusion barrier).Type: ApplicationFiled: January 3, 2019Publication date: July 9, 2020Applicant: INTEL CORPORATIONInventors: RAHUL RAMASWAMY, NIDHI NIDHI, WALID M. HAFEZ, JOHANN C. RODE, PAUL FISCHER, HAN WUI THEN, MARKO RADOSAVLJEVIC, SANSAPTAK DASGUPTA
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Publication number: 20200203484Abstract: A transistor is disclosed. The transistor includes a substrate, a superlattice structure that includes a plurality of heterojunction channels, and a gate that extends to one of the plurality of heterojunction channels. The transistor also includes a source adjacent a first side of the superlattice structure and a drain adjacent a second side of the superlattice structure.Type: ApplicationFiled: December 19, 2018Publication date: June 25, 2020Inventors: Nidhi NIDHI, Rahul RAMASWAMY, Sansaptak DASGUPTA, Han Wui THEN, Marko RADOSAVLJEVIC, Johann C. RODE, Paul B. FISCHER, Walid M. HAFEZ
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Publication number: 20200194575Abstract: Embodiments include a transistor and methods of forming such transistors. In an embodiment, the transistor comprises a semiconductor substrate, a barrier layer over the semiconductor substrate; a polarization layer over the barrier layer, an insulating layer over the polarization layer, a gate electrode through the insulating layer and the polarization layer, a spacer along sidewalls of the gate electrode, and a gate dielectric between the gate electrode and the barrier layer.Type: ApplicationFiled: December 13, 2018Publication date: June 18, 2020Inventors: Rahul RAMASWAMY, Nidhi NIDHI, Walid M. HAFEZ, Johann C. RODE, Paul FISCHER, Han Wui THEN, Marko RADOSAVLJEVIC, Sansaptak DASGUPTA
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Publication number: 20200194578Abstract: Embodiments include a transistor and methods of forming a transistor. In an embodiment, the transistor comprises a semiconductor channel, a source electrode on a first side of the semiconductor channel, a drain electrode on a second side of the semiconductor channel, a polarization layer over the semiconductor channel, an insulator stack over the polarization layer, and a gate electrode over the semiconductor channel. In an embodiment, the gate electrode comprises a main body that passes through the insulator stack and the polarization layer, and a first field plate extending out laterally from the main body.Type: ApplicationFiled: December 13, 2018Publication date: June 18, 2020Inventors: Rahul RAMASWAMY, Nidhi NIDHI, Walid M. HAFEZ, Johann C. RODE, Paul FISCHER, Han Wui THEN, Marko RADOSAVLJEVIC, Sansaptak DASGUPTA, Heli Chetanbhai VORA
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Publication number: 20200176582Abstract: An integrated circuit includes a gate structure in contact with a portion of semiconductor material between a source region and a drain region. The gate structure includes gate dielectric and a gate electrode. The gate dielectric includes at least two hybrid stacks of dielectric material. Each hybrid stack includes a layer of low-? dielectric and a layer of high-? dielectric on the layer of low-? dielectric, where the layer of high-? dielectric has a thickness at least two times the thickness of the layer of low-? dielectric. In some cases, the layer of low-? dielectric has a thickness no greater than 1.5 nm. The layer of high-? dielectric may be a composite layer that includes two or more layers of compositionally-distinct materials. The gate structure can be used with any number of transistor configurations but is particularly useful with respect to group III-V transistors.Type: ApplicationFiled: December 4, 2018Publication date: June 4, 2020Applicant: INTEL CORPORATIONInventors: Johann C. Rode, Samuel J. Beach, Nidhi Nidhi, Rahul Ramaswamy, Han Wui Then, Walid Hafez