Patents by Inventor Johann C. Rode

Johann C. Rode has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200219772
    Abstract: An integrated circuit structure and methodologies of forming same. In an embodiment, the integrated circuit structure includes a transistor gate structure in a first region of semiconductor material and a diode in a second region of the semiconductor material. The gate structure has a gate electrode of conductive material with a liner along sides and a bottom of the gate electrode. The gate electrode has a gate length less than a threshold dimension value. The diode includes a body of the conductive material in contact with the semiconductor material and includes the liner along sides of the body of conductive material. The body of conductive material has a lateral dimension greater than the threshold dimension value. The liner can include, for example, a gate dielectric and a diffusion barrier in some embodiments. In other embodiments, the liner is the gate dielectric (without any diffusion barrier).
    Type: Application
    Filed: January 3, 2019
    Publication date: July 9, 2020
    Applicant: INTEL CORPORATION
    Inventors: RAHUL RAMASWAMY, NIDHI NIDHI, WALID M. HAFEZ, JOHANN C. RODE, PAUL FISCHER, HAN WUI THEN, MARKO RADOSAVLJEVIC, SANSAPTAK DASGUPTA
  • Publication number: 20200203484
    Abstract: A transistor is disclosed. The transistor includes a substrate, a superlattice structure that includes a plurality of heterojunction channels, and a gate that extends to one of the plurality of heterojunction channels. The transistor also includes a source adjacent a first side of the superlattice structure and a drain adjacent a second side of the superlattice structure.
    Type: Application
    Filed: December 19, 2018
    Publication date: June 25, 2020
    Inventors: Nidhi NIDHI, Rahul RAMASWAMY, Sansaptak DASGUPTA, Han Wui THEN, Marko RADOSAVLJEVIC, Johann C. RODE, Paul B. FISCHER, Walid M. HAFEZ
  • Publication number: 20200194575
    Abstract: Embodiments include a transistor and methods of forming such transistors. In an embodiment, the transistor comprises a semiconductor substrate, a barrier layer over the semiconductor substrate; a polarization layer over the barrier layer, an insulating layer over the polarization layer, a gate electrode through the insulating layer and the polarization layer, a spacer along sidewalls of the gate electrode, and a gate dielectric between the gate electrode and the barrier layer.
    Type: Application
    Filed: December 13, 2018
    Publication date: June 18, 2020
    Inventors: Rahul RAMASWAMY, Nidhi NIDHI, Walid M. HAFEZ, Johann C. RODE, Paul FISCHER, Han Wui THEN, Marko RADOSAVLJEVIC, Sansaptak DASGUPTA
  • Publication number: 20200194578
    Abstract: Embodiments include a transistor and methods of forming a transistor. In an embodiment, the transistor comprises a semiconductor channel, a source electrode on a first side of the semiconductor channel, a drain electrode on a second side of the semiconductor channel, a polarization layer over the semiconductor channel, an insulator stack over the polarization layer, and a gate electrode over the semiconductor channel. In an embodiment, the gate electrode comprises a main body that passes through the insulator stack and the polarization layer, and a first field plate extending out laterally from the main body.
    Type: Application
    Filed: December 13, 2018
    Publication date: June 18, 2020
    Inventors: Rahul RAMASWAMY, Nidhi NIDHI, Walid M. HAFEZ, Johann C. RODE, Paul FISCHER, Han Wui THEN, Marko RADOSAVLJEVIC, Sansaptak DASGUPTA, Heli Chetanbhai VORA
  • Publication number: 20200176582
    Abstract: An integrated circuit includes a gate structure in contact with a portion of semiconductor material between a source region and a drain region. The gate structure includes gate dielectric and a gate electrode. The gate dielectric includes at least two hybrid stacks of dielectric material. Each hybrid stack includes a layer of low-? dielectric and a layer of high-? dielectric on the layer of low-? dielectric, where the layer of high-? dielectric has a thickness at least two times the thickness of the layer of low-? dielectric. In some cases, the layer of low-? dielectric has a thickness no greater than 1.5 nm. The layer of high-? dielectric may be a composite layer that includes two or more layers of compositionally-distinct materials. The gate structure can be used with any number of transistor configurations but is particularly useful with respect to group III-V transistors.
    Type: Application
    Filed: December 4, 2018
    Publication date: June 4, 2020
    Applicant: INTEL CORPORATION
    Inventors: Johann C. Rode, Samuel J. Beach, Nidhi Nidhi, Rahul Ramaswamy, Han Wui Then, Walid Hafez