Abstract: A data processing system including an input data port for receiving input data samples asynchronous to a native clock signal and having an input sample rate, a first sample rate converter for converting the data samples from the input sample rate to a sample rate synchronous with a rate of the native clock signal, and a data converter for converting data samples output from the first sample rate converter to another format. An analog to digital converter converts an analog signal into output data samples with a sample rate synchronous with the rate of the native clock signal, and a second sample rate converter converts the sample rate of the output data samples from the sample rate synchronous with the rate of the native clock signal to an output sample rate such that output data samples are asynchronous to the native clock signal.

Abstract: A pulse width modulation system including a pulse width modulation stage for generating a pulse width modulated signal in response to an input signal and an other pulse width modulation stage for generating an other pulse width modulated signal in response to an other input signal. Additional circuitry ensures that transitions of the pulse width modulated signal and the other pulse width modulated signal are spaced in time by a selected amount for small levels of the input signal.

Abstract: A pulse width modulation circuit for driving a full-bridge output load includes a pulse width modulation stage for generating, from an input data stream, a pulse width modulated data stream for driving a terminal of a full-bridge output load and another pulse width modulated data stream for driving another terminal of the full bridge output load. A delay circuit delays the another pulse width modulated data stream relative to the pulse width modulated data stream such that edges of the another pulse width modulated data stream and edges of the pulse width modulated data stream are temporally spaced.

Abstract: An output driver circuit including a transistor for pulling down an output terminal voltage and a charge pump for driving an input of the transistor to pull-down the output terminal voltage substantially to zero volts in response to a selected level of an input signal.

Abstract: A system for suppressing transient noise in switched-mode amplifier systems is disclosed. An amplifier, for amplifying a signal from a digital signal source includes a first complementary metal oxide semiconductor field effect transistor (MOSFET) pair. A common node of the pair is serially coupled to an output node of the amplifier by a resistor. The first MOSFET pair is configured to drive a ramp on the output node of the amplifier.

Abstract: An output stage 300 includes a first output switch 201 having a current path for driving an output from a first voltage rail and a second output switch 202 having a current path for selectively driving the output from a second voltage rail. A first reference switch 301 is scaled with respects to first output switch 201 and has a current path coupled to the first voltage rail. A second reference switch 302 scaled with respects to second output switch 202 has a current path coupled to a current path of first reference switch 301 at a node and the second voltage rail. The logic measures an impedance mismatch between first and second reference switches 301, 302 and proportionally varies the impedance of a selected one of first and second output switches 201, 202 in response.

Abstract: An apparatus and method for power digital-to-analog converter protection are implemented. An attenuation value is set in response to the value of the supply voltage. The attenuation value is provided to a gain control, along with the input signal. A gain, offset by the attenuation value, determines the gain-adjusted output signal of the gain control generated from the input signal.

Abstract: A multirate digital-to-analog amplifier system is disclosed. An interpolator is configured to interpolate digital values between samples of a digital signal from a digital signal source, in which the digital signal has a first sample rate. An output signal from the interpolator has a second, predetermined sample rate, which is independent of the first sample rate, of the digital signal. An amplifier is configured to amplify a digital signal having the second sample rate in response to the output signal of the interpolator.

Abstract: Circuitry for selectively sampling a reference voltage with a capacitor 403 includes a first switch 505a for selectively coupling capacitor 403 to a source of a first reference signal during a first operating phase and a second switch 505b for selectively coupling capacitor 403 to a source of a second reference signal during a second operating phase.