Abstract: A MEMS device and a method for manufacturing a MEMS device are disclosed. In an embodiment the MEMS device comprises a support having a cavity therethrough and a membrane extended over the cavity of the support, wherein the membrane is at least partially reinforced by graphene.

Abstract: A MEMS device and a method for manufacturing a MEMS device are disclosed. In an embodiment the MEMS device comprises a support having a cavity therethrough and a membrane extended over the cavity of the support, wherein the membrane is at least partially reinforced by graphene.

Abstract: A driver circuit having series-connected high-side and low-side MOS switches with MOS transistors for driving a load, a temperature-limiting circuit and a current-limiting circuit, which is assigned to one of the two MOS transistors. In order to balance power losses between the high-side and low-side MOS switches, provision is made for the gate of the MOS transistor without the current-limiting circuit to be connected to ground via a voltage generator, whose voltage corresponds to a maximum drive voltage for this MOS transistor.

Abstract: A circuit configuration for triggering a field effect transistor with a source-side load has a capacitor which is connected on one hand through a load path of the field effect transistor to a supply voltage and on the other hand both to a first charging device and to a first controllable switching device. The first switching device is connected between the capacitor and a gate terminal of the field effect transistor. A second charging device acts through a second controllable switching device to charge a gate-to-source capacitor of the field effect transistor. A comparator monitors a voltage at the gate terminal of the field effect transistor and makes the first switching device conducting when a predetermined value is reached.

Abstract: An analog delay circuit configuration includes a switching stage. A capacitor is connected upstream of the switching stage. A controlled current source has a current being definitive for a charging state of the capacitor. The current source is clocked with a pulse-to-interval ratio of less than 1. A current mirror configuration reduces the current of the current source. An inverter stage is coupled to the current mirror configuration and has an output side connected to the capacitor.

Abstract: A circuit configuration for monitoring the temperature of power switching transistor integrated in a semiconductor circuit for overload protection includes temperature sensors each being associated with one respective power switching transistor for detecting the circuit temperature and issuing an output signal. Comparison stages are each connected to a respective one of the temperature sensors for comparing the output signal of one of the temperature sensors with a first reference corresponding to a first predetermined temperature value and switching off only the power switching transistor associated therewith upon attainment of the first predetermined temperature value.