Abstract: A memory module has a memory cell configuration. For the purpose of testing the memory cell configuration, the memory module has a test structure with at least two test circuits, which are disposed in a distributed fashion on the memory module and are connected to one another via a common test switching bus, which can be connected to an address bus of the memory module via a decoupling circuit during a test operation.

Abstract: The testing of a RAM memory circuit containing a multiplicity of memory cells can in each case be selected in groups of n?1 memory cells by using an applied address information item in order to write in or read out groups of in each case n data. According to the invention, in a test write cycle, a plurality i=j*m of the memory cell groups are selected, where j and m are in each case integers ?2, and the same datum is written into all the memory cells of in each case m selected memory cell groups. In a subsequent read cycle, the i memory cell groups selected in the write cycle are selected and read in a sequence such that the read-out data groups from in each case m memory cell groups at which the same datum was written in are provided simultaneously or in direct succession as a read data block comprising m*n data.

Abstract: An integrated semiconductor memory including memory cells which can be driven via first and second word lines and can be replaced by redundant memory cells. In the first memory cell type, data can be stored corresponding to the data present at a data input terminal. In the memory cells of a second memory cell type, data can be stored inverted with respect to data present at the data input terminal. The integrated semiconductor memory includes a circuit for data inversion, wherein the data are written to a redundant memory cell, inverted with respect to the data present at the data input terminal if the defective memory cell and the redundant memory cell replacing it are situated in different word line strips of a bit line twist, and if the defective memory cell and the redundant memory cell replacing it are associated with different memory cell types.

Abstract: An integrated circuit with a test circuit having a measurement converter circuit and an activation unit. The measurement converter circuit converts one or more circuit-internal signals into a measured value. The activation unit activates the measurement converter circuit in accordance with an activation signal. The measurement converter circuit and the activation unit are connected to a connection pad. The activation unit is configured in such a way as to switch on the measurement converter circuit by means of the activation signal received via the connection pad. The measured value can be tapped off via the connection pad.

Abstract: A memory circuit comprises a memory and an internal column counter for a read sequence in a compression test mode of the memory. The memory comprises an array of memory cells. The internal column counter is configured to provide a first column address for generating a compression register of expected data to compare to data read from the array of memory cells in response to a first read command, latch a second column address in response to a second read command while the first read command is executing, and provide the second column address for generating the compression register of expected data to compare to data read from the array of memory cells in response to the second read command once execution of the first read command is completed.

Abstract: The invention refers to a circuit device (1) with at least one connection (3b), to which a clock pulse (/CLK, /CLKT) can be applied, whereby the circuit device (1) also comprises a clock pulse detection facility (2) for detecting whether there is a clock pulse (/CLK, /CLKT) present at the connection (3b), or whether there is no clock pulse (/CLK, /CLKT) present at the connection (3b).

Abstract: A memory circuit comprises a memory and an internal column counter for a read sequence in a compression test mode of the memory. The memory comprises an array of memory cells. The internal column counter is configured to provide a first column address for generating a compression register of expected data to compare to data read from the array of memory cells in response to a first read command, latch a second column address in response to a second read command while the first read command is executing, and provide the second column address for generating the compression register of expected data to compare to data read from the array of memory cells in response to the second read command once execution of the first read command is completed.

Abstract: A digital memory circuit has at least two pairs of adjacent memory banks. Each of the banks has n parallel terminals for n read/write data lines. Each bank pair has only two bundles of n/2 read/write data lines. A first bundle is assigned to the first half of a first bank and to a second half of a second bank and the second bundle is assigned to a second half of the first bank and to a first half of the second bank. Data are input/output in parallel to n/2 input/output lines with the timing of successive half-periods of a clock signal. A changeover device is changeable between different switching states for connecting a bundle of n/2 input/output lines to the read/write data lines of the bank pair containing the addressed bank, depending on whether the data are assigned to the first or second half-period of the clock signal.

Abstract: A semiconductor circuit has at least one generator fuse for setting a supply voltage and at least one redundancy fuse for activating a redundancy element. A first read-out device is provided for reading out the generator fuse and a second read-out device reads out the redundancy fuse. The first read-out device is configured to read out the generator fuse at a first instant, and the second read-out device is configured to read out the redundancy fuse at a second instant.

Abstract: The invention relates to a method for reducing the current consumption of an electronic circuit having at least one test module for testing the electronic circuit. The test module is connected to at least one line and/or a connection of the electronic circuit. A test control signal is generated, by means of which the test module is at least partially decoupled from the line or the connection in an operating mode of the electronic circuit such that switching currents are prevented in the test module.

Abstract: The invention relates to a method for configuring a network termination unit for the packet-by-packet asynchronous transfer mode transmission of data. According to said method data subdivided into cells and assembled into packets are transmitted either at a constant data rate (CBR), for example in the case of voice or video data, or at a non-constant data rate (UBR). The data cells or packets are received and transmitted via the network termination unit, which constitutes an interface between a transmission line and data terminal. The number of data cells contained in each transmitted or received data packet is determined in the network unit (10) and from this number it is determined whether the ATM connection is carried out at a constant (CBR) or non-constant (UBR) data rate. The data packets of a CBR connection have processing priority over the data packets of a UBR connection.

Abstract: Integrated module having a circuit and a plurality of input/output terminals, each of the input/output terminals being connected to a driver circuit for driving output signals and to a reception circuit for receiving input signals, a first delay element with a first delay time being provided in the integrated module, which delay element can be connected into a signal path of a circuit-internal signal or can be disconnected, in order to delay or to accelerate the circuit-internal signal, wherein provision is made of a first test delay element at a first input/output terminal pair which is embodied in a manner structurally identical to the first delay element, in order, in a test operation, to determine the delay time by means of the signal propagation time between the two input/output terminals of the first input/output terminal pair.

Abstract: One embodiment of the invention provides a RAM memory circuit having k?2 banks, each of which having a multiplicity of memory cells and a selection device to simultaneously select groups of in each case n?2 memory cells of the bank for the writing or reading of n parallel data. For the fast testing of all the banks, devices are included for the parallel switching of the banks such that reading and writing may be effected simultaneously at all the banks. For each bank, a dedicated evaluation device is included for comparing the n data respectively read out at the relevant bank with a reference information item, which is representative of the write data which have previously been written in at the currently selected memory cell group of the bank, and for providing a result information item, comprising 1?m?n/k bits, each of which indicates whether a subset precisely assigned to it from m subsets of the n read data corresponds to a part of the reference information item which is precisely assigned to said subset.

Abstract: A semiconductor memory includes: at least two memory banks that each have a memory cell matrix, an address decoding unit which includes a bank address decoding unit, a row address decoding unit and a column address decoding unit. At least one demultiplexer is connected upstream of the address buffer memories provided in the row address decoding unit and/or in the column address decoding unit. This demultiplexer is connected to the bank address decoder in order, on the basis of the decoded bank address, to activate the corresponding address buffer memory.

Abstract: An integrated semiconductor memory including memory cells which can be driven via first and second word lines and can be replaced by redundant memory cells. In the first memory cell type, data can be stored corresponding to the data present at a data input terminal. In the memory cells of a second memory cell type, data can be stored inverted with respect to data present at the data input terminal. The integrated semiconductor memory includes a circuit for data inversion, wherein the data are written to a redundant memory cell, inverted with respect to the data present at the data input terminal if the defective memory cell and the redundant memory cell replacing it are situated in different word line strips of a bit line twist, and if the defective memory cell and the redundant memory cell replacing it are associated with different memory cell types.

Abstract: A RAM memory circuit has at least one memory bank with a multiplicity of memory cells arranged like a matrix in rows and columns and is subdivided into q?2 areas, each of which comprises p?1 segments each comprising a plurality of columns. Each segment is assigned a bundle of master data lines, which branches from an area bus assigned to the relevant area and, for its part, branches via a switching network to the memory cells of the relevant segment. The area buses can be connected cyclically to a common data port. In order to allow a read operation the beginning of which overlaps the end of a preceding write operation, each master data line bundle has coupled to it a data latch for holding the data respectively appearing there, and an isolating switch is in each case provided between each master data line bundle and the assigned area bus.

Abstract: One embodiment of the invention provides a RAM memory circuit having k?2 banks, each of which having a multiplicity of memory cells and a selection device to simultaneously select groups of in each case n?2 memory cells of the bank for the writing or reading of n parallel data. For the fast testing of all the banks, devices are included for the parallel switching of the banks such that reading and writing may be effected simultaneously at all the banks. For each bank, a dedicated evaluation device is included for comparing the n data respectively read out at the relevant bank with a reference information item, which is representative of the write data which have previously been written in at the currently selected memory cell group of the bank, and for providing a result information item, comprising 1?m?n/k bits, each of which indicates whether a subset precisely assigned to it from m subsets of the n read data corresponds to a part of the reference information item which is precisely assigned to said subset.

Abstract: The invention involves a component with a connection (3b), as well as at least one further connection (3a), whereby differential input clock pulses (CLK, CLKT; /CLK, /CLKT) can be applied to the connections (3a, 3b), or a single input clock pulse (CLK, CLKT) applied to the connection (3b) and/or to the further connection (3a)—, and where the component in addition has a first and a second pulse relay device (50, 51), where the first pulse relay device (50) has been provided for relaying differential input clock pulses (CLK, CLKT; /CLK, /CLKT), and the second pulse relay device (51) for relaying a single input clock pulse (CLK, CLKT).

Abstract: An integrated memory contains an access controller for controlling an access for the purpose of reading data from, or writing data to, a memory cell array. The access controller accesses the memory cell array in a first double data rate operating mode of the memory in such a manner that a first data item (which is to be written) of an access cycle is written to the memory cell array with a write latency. In a second single data rate operating mode of the memory, the access controller, in contrast, accesses the memory cell array in such a manner that a first data item of an access cycle is, in contrast, written to the memory cell array in an accelerated manner without the write latency of the first operating mode. This makes it possible to read in data values in an accelerated manner in the second operating mode, in particular a test operating mode.

Abstract: The invention relates to a semiconductor memory element comprising a plurality of data pins and at least two memory cell arrays, each of which comprises a plurality of memory cells, and each of which is connected to an array logic for reading in and/or reading out data into or from the respective array, wherein the data pins or interface circuits connected therewith are directly connected to the respective array logic.