Abstract: Methods for forming an integrated semiconductor circuit arrangement are disclosed. In one embodiment, a semiconductor circuit with a first semiconductor circuit region and with a second semiconductor circuit region is formed in each case in a semiconductor material region. A first metallization layer is applied to the structure thus obtained. A protective material region is then formed. A second metallization layer is subsequently applied, which is then also patterned. Afterward, the first metallization layer together with the protective material region is then patterned.

Abstract: Methods for forming an integrated semiconductor circuit arrangement are disclosed. In one embodiment, a semiconductor circuit with a first semiconductor circuit region and with a second semiconductor circuit region is formed in each case in a semiconductor material region. A first metallization layer is applied to the structure thus obtained. A protective material region is then formed. A second metallization layer is subsequently applied, which is then also patterned. Afterward, the first metallization layer together with the protective material region is then patterned.

Abstract: A method for checking a semiconductor memory device integrated on a semiconductor chip includes providing the semiconductor memory device with a plurality of memory cells each being disposed on a semiconductor substrate for one binary information value, data lines for reading out and writing in information values, gate transistors being associated with the memory cells for selectively clearing a data path between a given memory cell and a data line, selection lines for purposefully triggering the gate transistors, and at least one in-chip reference voltage being adjusted to a predetermined normal value when the semiconductor memory device is functioning as intended. The method for checking the semiconductor memory device integrated on a semiconductor chip is carried out by at least intermittently varying the at least one in-chip reference voltage, and detecting and weighting the information values read out at the at least intermittently varied reference voltage.

Abstract: A method for checking a semiconductor memory device integrated on a semiconductor chip includes providing the semiconductor memory device with a plurality of memory cells each being disposed on a semiconductor substrate for one binary information value, data lines for reading out and writing in information values, gate transistors being associated with the memory cells for selectively clearing a data path between a given memory cell and a data line, selection lines for purposefully triggering the gate transistors, and at least one in-chip reference voltage being adjusted to a predetermined normal value when the semiconductor memory device is functioning as intended. The method for checking the semiconductor memory device integrated on a semiconductor chip is carried out by at least intermittently varying the at least one in-chip reference voltage, and detecting and weighting the information values read out at the at least intermittently varied reference voltage.

Abstract: A DRAM with an address space divided into blocks, in which storage cells of individual blocks can be activated by a row address signal (RAS) furnished by a controller. Each individual block can then be activated by an independent activation signal derived from the row address signal. The activation signals for different blocks are supplied to the different blocks in succession with a partial time overlap, so that the obtained data rate is increased relative to activation of only one block, owing to partial time activation of at least two different blocks.

Abstract: A bootstrap circuit includes a transfer transistor and a driver transistor of the same channel type each having two channel terminals and a gate. A first signal terminal receives a first signal and a second signal terminal receives a second signal. One of the channel terminals of the transfer transistor is connected to the gate of the driver transistor. The other of the channel terminals of the transfer transistor is connected to the first signal terminal. One of the channel terminals of the driver transistor is connected to the second signal terminal. The other of the channel terminals of the driver transistor forms an output of the bootstrap circuit. A configuration generates a third signal and has an output connected to the gate of the transfer transistor. The second signal has an edge extending from a first level to a second level and beginning at a bootstrap time.

Abstract: An evaluation and amplifier circuit of the type of a keyed flipflop including at least two first transistors of a given channel type connected in series to each other disposed between first and second signal lines, has a connection from the gates of the first transistors to a respective one of the second and first signal lines. The first two transistors respectively form a first node common to the first two transistors for receiving a first control signal. A series circuit has at least two second transistors of the same channel type as the first transistors being connected in parallel to the first transistors, The gates of the first transistors are further connected with a respective one of the second and first signal lines.

Abstract: Integrated semiconductor memory device having a semiconductor substrate with a redundant circuit arrangement formed thereon for replacing a defective memory cell of the integrated semiconductor memory device by selecting a redundant memory cell likewise disposed on the semiconductor substrate, the memory cells of the integrated semiconductor memory device being constructed and addressable in blocks; the redundant memory cells being combined into a redundant memory cell field addressable as a unit by the redundant circuit arrangement; and the redundant circuit arrangement having a redundant selection circuit for selecting a redundant memory cell from the redundant memory cell field to replace a defective memory cell from any of the memory cell blocks, includes a redundance control circuit forming part of the redundant circuit arrangement and enabling, as a function of a programmed redundant selection signal, one of the data content of a normal memory cell and the data content of a redundant memory cell suitabl

Abstract: Integrated semiconductor memory having normal memory cells arranged at intersections of word lines and bit lines, decoders for selecting a word line as a function of applicable word line address signals decoders for selecting a bit line as a function of applicable bit line address signals, external reading and evaluator circuits associated with the bit lines of the normal memory cells and connected on an output side thereof with data lines whereat data content is to be output, and redundant memory cells, additionally, by at least one programmable redundant decoder for replacing a defective memory cell, includes external redundant reading and evaluator circuits triggerable by the at least one programmable redundant decoder and associated with the redundant memory cells, the external redundant reading and evaluator circuits being connectible on the input side with the redundant memory cells and on the output side with the data lines, and a redundant control circuit associated with each of the external redundant

Abstract: A semiconductor component includes a semiconductor body having a terminal pad, a semiconductor function element, and an electrically conductive connecting line connecting the terminal pad to the semiconductor function element. A protective element for protecting against electrostatic discharge is connected between the terminal pad and the semiconductor function element. A first supply line for a first supply potential is connected to the semiconductor function element. A second supply line for the first supply potential is connected to the protective element and is electrically conductively connected to the first supply line. A clamp element is connected to the connecting line and to the first supply line, for limiting a voltage applied to the clamp element to a clamp value.

Abstract: An integrated semiconductor memory has a block decoder BKDEC having block selection signals BKS and a plurality of main memory area block units BK which can be individually activated. The main memory area block units BK contain memory locations which can be selected via word and bit lines NWL, NBL, NBL and redundancy memory locations RMC, which can be selected via redundancy word lines RWL. The main memory area block units BK contain programmable redundancy block decoders RBK, which in conjunction with redundancy word line decoders RWDEC enable the selection of redundancy word lines RWL. If a redundancy word line RWL is to be selected, it is exclusively that main memory area block unit BK in which the redundancy word line RWL that is to be selected is contained that is activated. In this case, activation which is otherwise usual is suppressed via an appropriate block selection signal BKS.

Abstract: A viscous shear coupling for distributing torque between front and rear axles of an all-wheel drive vehicle is provided which comprises a housing, a set of inner blades interdigitating with a set of outer blades, the inner and outer blades being axially spaced apart from each other and axially slidably mounted within the housing, a viscous liquid located within the housing, an adjusting piston within the housing which is axially displaceable so as to adjust the axial distance between adjacent inner and outer blades. The viscous shear coupling further includes a control pressure circuit for delivery of a control pressure fluid to the adjusting piston, a control valve for regulating the delivery of the control pressure fluid to the adjusting piston, and a control device (e.g., a microprocessor) which calculates a desired adjusting piston speed based on driving conditions and adjusts a valve current delivered to the control valve in order to obtain the desired adjusting piston speed.

Abstract: A railway structure for a sliding chair (2), a sliding plate and a ribbed plate (1), respectively, for railway switches or railway crossings. The structure includes friction-reducing sliding members (4, 5) of synthetic plastic material being releasably mounted within recesses (3) in the sliding chair (2) and the plates, respectively. There are accommodated within each recess (3) at least two sliding members (4, 5) having their side surfaces engaged over the major part of the periphery by inwardly protruding walls or profiles of the edge of the recess, so that there results a safe mounting in position of the sliding members (4, 5). The structure makes the interchange of the sliding members a simple procedure.

Abstract: In a device for fixing stock rails (1) in railway switches, including a base plate (2) for the stock rail (1) and a sliding chair (3) for the switch tongue mounted on the base plate and comprising an elongated spring element (6) for pressing down the rail foot and preferably having the shape of a plate, the spring element (6) can be introduced, preferably without tension, into a tunnel-shaped recess (5) provided in the sliding chair (3) and extending in a direction approximately normal to the stock rail. The upper edge of the tongue-shaped recess (5) within the sliding chair (3) extends, with the formation of a kink (13), in direction towards the rail foot steeper in upward direction that in an area (11) extending more flatly in front of the kink (13). A separate wedge (10) can, for the purpose of guying the spring element (6) against the rail foot, be driven in within the area (11) of flatter extension of the upper edge at a distance from the kink (13) of the upper edge.

Abstract: In an arrangement for fastening stock rails, wing rails or track rails (1) at the side being averted from the running edge, in which arrangement a strap (5) is pressed against the web of the rail with interposition of a leaf spring (9) or, respectively, of a spring pile, the strap (5) is given a convex shape at its outer side facing the leaf spring (9), whereby a defined pressure point (D) is provided for the attack of the leaf spring (9).

Abstract: A DRAM with an address space divided into blocks, in which storage cells of individual blocks can be activated by a row address signal (RAS) furnished by a controller. Each individual block can then be activated by an independent activation signal derived from the row address signal. The activation signals for different blocks are supplied to the different blocks in succession with a partial time overlap, so that the obtained data rate is increased relative to activation of only one block, owing to partial time activation of at least two different blocks.