Patents by Inventor Johanna M. Swan

Johanna M. Swan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12288751
    Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate including a dielectric material having a first surface and an opposing second surface, a first material on at least a portion of the second surface, and a second material on at least a portion of the first material, wherein the second material has a different material composition than the first material.
    Type: Grant
    Filed: August 17, 2023
    Date of Patent: April 29, 2025
    Assignee: Intel Corporation
    Inventors: Aleksandar Aleksov, Johanna M. Swan
  • Patent number: 12266682
    Abstract: Disclosed herein are capacitors and resistors at direct bonding interfaces in microelectronic assemblies, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component, wherein a direct bonding interface of the second microelectronic component is direct bonded to a direct bonding interface of the first microelectronic component, the microelectronic assembly includes a sensor, the sensor includes a first sensor plate and a second sensor plate, the first sensor plate is at the direct bonding interface of the first microelectronic component, and the second sensor plate is at the direct bonding interface of the second microelectronic component.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: April 1, 2025
    Assignee: Intel Corporation
    Inventors: Adel A. Elsherbini, Mohammad Enamul Kabir, Zhiguo Qian, Gerald S. Pasdast, Kimin Jun, Shawna M. Liff, Johanna M. Swan, Aleksandar Aleksov, Feras Eid
  • Patent number: 12261097
    Abstract: Disclosed herein are structures and assemblies that may be used for thermal management in integrated circuit (IC) packages.
    Type: Grant
    Filed: August 8, 2023
    Date of Patent: March 25, 2025
    Assignee: Intel Corporation
    Inventors: Feras Eid, Telesphor Kamgaing, Georgios Dogiamis, Aleksandar Aleksov, Johanna M. Swan
  • Publication number: 20250096194
    Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.
    Type: Application
    Filed: December 2, 2024
    Publication date: March 20, 2025
    Applicant: Intel Corporation
    Inventors: Shawna M. Liff, Adel A. Elsherbini, Johanna M. Swan, Arun Chandrasekhar
  • Publication number: 20250070083
    Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include: a first die having a first surface and an opposing second surface, first conductive contacts at the first surface of the first die, and second conductive contacts at the second surface of the first die; and a second die having a first surface and an opposing second surface, and first conductive contacts at the first surface of the second die; wherein the second conductive contacts of the first die are coupled to the first conductive contacts of the second die by interconnects, the second surface of the first die is between the first surface of the first die and the first surface of the second die, and a footprint of the first die is smaller than and contained within a footprint of the second die.
    Type: Application
    Filed: November 8, 2024
    Publication date: February 27, 2025
    Inventors: Adel A. ELSHERBINI, Henning BRAUNISCH, Aleksandar ALEKSOV, Shawna M. LIFF, Johanna M. SWAN, Patrick MORROW, Kimin JUN, Brennen MUELLER, Paul B. FISCHER
  • Publication number: 20250040231
    Abstract: Gallium nitride (GaN) three-dimensional integrated circuit technology is described. In an example, an integrated circuit structure includes a layer including gallium and nitrogen, a plurality of gate structures over the layer including gallium and nitrogen, a source region on a first side of the plurality of gate structures, a drain region on a second side of the plurality of gate structures, the second side opposite the first side, and a drain field plate above the drain region wherein the drain field plate is coupled to the source region. In another example, a semiconductor package includes a package substrate. A first integrated circuit (IC) die is coupled to the package substrate. The first IC die includes a GaN device layer and a Si-based CMOS layer.
    Type: Application
    Filed: October 14, 2024
    Publication date: January 30, 2025
    Inventors: Han Wui THEN, Marko RADOSAVLJEVIC, Pratik KOIRALA, Nicole K. THOMAS, Paul B. FISCHER, Adel A. ELSHERBINI, Tushar TALUKDAR, Johanna M. SWAN, Wilfred GOMES, Robert S. CHAU, Beomseok CHOI
  • Publication number: 20250022845
    Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface; a first die having a first surface and an opposing second surface embedded in a first dielectric layer, where the first surface of the first die is coupled to the second surface of the package substrate by first interconnects; a second die having a first surface and an opposing second surface embedded in a second dielectric layer, where the first surface of the second die is coupled to the second surface of the first die by second interconnects; and a third die having a first surface and an opposing second surface embedded in a third dielectric layer, where the first surface of the third die is coupled to the second surface of the second die by third interconnects.
    Type: Application
    Filed: September 6, 2024
    Publication date: January 16, 2025
    Inventors: Adel A. Elsherbini, Feras Eid, Johanna M. Swan, Shawna M. Liff
  • Patent number: 12199018
    Abstract: Disclosed herein are microelectronic assemblies including direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes a first subregion and a second subregion, and the first subregion has a greater metal density than the second subregion. In some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes a first metal contact and a second metal contact, the first metal contact has a larger area than the second metal contact, and the first metal contact is electrically coupled to a power/ground plane of the first microelectronic component.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: January 14, 2025
    Assignee: Intel Corporation
    Inventors: Adel A. Elsherbini, Krishna Bharath, Han Wui Then, Kimin Jun, Aleksandar Aleksov, Mohammad Enamul Kabir, Shawna M. Liff, Johanna M. Swan, Feras Eid
  • Patent number: 12199063
    Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.
    Type: Grant
    Filed: January 3, 2024
    Date of Patent: January 14, 2025
    Assignee: Intel Corporation
    Inventors: Shawna M. Liff, Adel A. Elsherbini, Johanna M. Swan, Arun Chandrasekhar
  • Publication number: 20250006695
    Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first layer with a first die having a first contact; a second die having a second contact; and a pad layer, on the first and second dies, including a first pad and a second pad, where the first pad is coupled to and offset from the first contact in a first direction, and the second pad is coupled to and is offset from the second contact in a second direction different than the first direction; and a second layer including a third die having third and fourth contacts, where the first layer is coupled to the second layer by metal-to-metal bonds and fusion bonds, the first contact is coupled to the third contact by the first pad, and the second contact is coupled to the fourth contact by the second pad.
    Type: Application
    Filed: June 29, 2023
    Publication date: January 2, 2025
    Applicant: Intel Corporation
    Inventors: Bhaskar Jyoti Krishnatreya, Adel A. Elsherbini, Brandon M. Rawlings, Kimin Jun, Omkar G. Karhade, Mohit Bhatia, Nitin A. Deshpande, Prashant Majhi, Johanna M. Swan
  • Patent number: 12183961
    Abstract: A method of forming a waveguide comprises forming an elongate waveguide core including a dielectric material; and arranging a conductive sheet around an outside surface of the dielectric core to produce a conductive layer around the waveguide core.
    Type: Grant
    Filed: August 16, 2021
    Date of Patent: December 31, 2024
    Assignee: Intel Corporation
    Inventors: Aleksandar Aleksov, Georgios C. Dogiamis, Telesphor Kamgaing, Sasha N. Oster, Adel A. Elsherbini, Shawna M. Liff, Johanna M. Swan, Brandon M. Rawlings, Richard J. Dischler
  • Publication number: 20240429173
    Abstract: A multi-chip package includes a substrate (110) having a first side (111), an opposing second side (112), and a third side (213) that extends from the first side to the second side, a first die (120) attached to the first side of the substrate and a second die (130) attached to the first side of the substrate, and a bridge (140) adjacent to the third side of the substrate and attached to the first die and to the second die. No portion of the substrate is underneath the bridge. The bridge creates a connection between the first die and the second die. Alternatively, the bridge may be disposed in a cavity (615, 915) in the substrate or between the substrate and a die layer (750). The bridge may constitute an active die and may be attached to the substrate using wirebonds (241, 841, 1141, 1541).
    Type: Application
    Filed: September 3, 2024
    Publication date: December 26, 2024
    Inventors: Henning BRAUNISCH, Chia-Pin CHIU, Aleksandar ALEKSOV, Hinmeng AU, Stefanie M. LOTZ, Johanna M. SWAN, Sujit SHARAN
  • Patent number: 12176323
    Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include: a first die having a first surface and an opposing second surface, first conductive contacts at the first surface of the first die, and second conductive contacts at the second surface of the first die; and a second die having a first surface and an opposing second surface, and first conductive contacts at the first surface of the second die; wherein the second conductive contacts of the first die are coupled to the first conductive contacts of the second die by interconnects, the second surface of the first die is between the first surface of the first die and the first surface of the second die, and a footprint of the first die is smaller than and contained within a footprint of the second die.
    Type: Grant
    Filed: April 25, 2022
    Date of Patent: December 24, 2024
    Assignee: Intel Corporation
    Inventors: Adel A. Elsherbini, Henning Braunisch, Aleksandar Aleksov, Shawna M. Liff, Johanna M. Swan, Patrick Morrow, Kimin Jun, Brennen Mueller, Paul B. Fischer
  • Patent number: 12165962
    Abstract: Disclosed herein are microelectronic assemblies including microelectronic components coupled by direct bonding, and related structures and techniques. In some embodiments, a microelectronic assembly may include a first microelectronic component including a first guard ring extending through at least a portion of a thickness of and along a perimeter; a second microelectronic component including a second guard ring extending through at least a portion of a thickness of and along a perimeter, where the first and second microelectronic components are coupled by direct bonding; and a seal ring formed by coupling the first guard ring to the second guard ring. In some embodiments, a microelectronic assembly may include a microelectronic component coupled to an interposer that includes a first liner material at a first surface; a second liner material at an opposing second surface; and a perimeter wall through the interposer and connected to the first and second liner materials.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: December 10, 2024
    Assignee: Intel Corporation
    Inventors: Aleksandar Aleksov, Mohammad Enamul Kabir, Adel A. Elsherbini, Shawna M. Liff, Johanna M. Swan, Feras Eid
  • Patent number: 12155372
    Abstract: Embodiments may relate to a die such as an acoustic wave resonator (AWR) die. The die may include a first filter and a second filter in the die body. The die may further include an electromagnetic interference (EMI) structure that surrounds at least one of the filters. Other embodiments may be described or claimed.
    Type: Grant
    Filed: March 7, 2022
    Date of Patent: November 26, 2024
    Assignee: Intel Corporation
    Inventors: Georgios Dogiamis, Aleksandar Aleksov, Feras Eid, Telesphor Kamgaing, Johanna M. Swan
  • Patent number: 12150271
    Abstract: Embodiments may relate an electronic device that includes a first server blade and a second server blade coupled with a chassis. The first and second server blades may include respective microelectronic packages. The electronic device may further include a waveguide coupled to the first and second server blades such that their respective microelectronic packages are communicatively coupled by the waveguide. Other embodiments may be described or claimed.
    Type: Grant
    Filed: June 8, 2023
    Date of Patent: November 19, 2024
    Assignee: Intel Corporation
    Inventors: Telesphor Kamgaing, Johanna M. Swan, Georgios Dogiamis, Henning Braunisch, Adel A. Elsherbini, Aleksandar Aleksov, Richard Dischler
  • Patent number: 12148747
    Abstract: Gallium nitride (GaN) three-dimensional integrated circuit technology is described. In an example, an integrated circuit structure includes a layer including gallium and nitrogen, a plurality of gate structures over the layer including gallium and nitrogen, a source region on a first side of the plurality of gate structures, a drain region on a second side of the plurality of gate structures, the second side opposite the first side, and a drain field plate above the drain region wherein the drain field plate is coupled to the source region. In another example, a semiconductor package includes a package substrate. A first integrated circuit (IC) die is coupled to the package substrate. The first IC die includes a GaN device layer and a Si-based CMOS layer.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: November 19, 2024
    Assignee: Intel Corporation
    Inventors: Han Wui Then, Marko Radosavljevic, Pratik Koirala, Nicole K. Thomas, Paul B. Fischer, Adel A. Elsherbini, Tushar Talukdar, Johanna M. Swan, Wilfred Gomes, Robert S. Chau, Beomseok Choi
  • Patent number: 12142510
    Abstract: Described herein are carrier assemblies, and related devices and methods. In some embodiments, a carrier assembly includes a carrier; a textured material including texturized microstructures coupled to the carrier; and microelectronic components mechanically coupled to the texturized microstructures. In some embodiments, a carrier assembly includes a carrier having a front side and a back side; an electrode on the front side of the carrier; a dielectric material on the electrode; a charging contact on the back side coupled to the electrode; and microelectronic components electrostatically coupled to the front side of the carrier. In some embodiments, a carrier assembly includes a carrier having a front side and a back side; electrodes on the front side; a dielectric material including texturized microstructures on the electrodes; charging contacts on the back side coupled to the plurality of electrodes; and microelectronic components mechanically and electrostatically coupled to the front side of the carrier.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: November 12, 2024
    Assignee: Intel Corporation
    Inventors: Shawna M. Liff, Johanna M. Swan, Adel A. Elsherbini, Michael J. Baker, Aleksandar Aleksov, Feras Eid
  • Patent number: 12136596
    Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate including a dielectric material having a first surface and an opposing second surface, a first material on at least a portion of the second surface, and a second material on at least a portion of the first material, wherein the second material has a different material composition than the first material.
    Type: Grant
    Filed: September 28, 2023
    Date of Patent: November 5, 2024
    Assignee: Intel Corporation
    Inventors: Aleksandar Aleksov, Johanna M. Swan
  • Publication number: 20240355768
    Abstract: Disclosed herein are microelectronic assemblies including microelectronic components that are coupled together by direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component and a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes at least part of an inductor.
    Type: Application
    Filed: July 2, 2024
    Publication date: October 24, 2024
    Applicant: Intel Corporation
    Inventors: Adel A. Elsherbini, Krishna Bharath, Kevin P. O'Brien, Kimin Jun, Han Wui Then, Mohammad Enamul Kabir, Gerald S. Pasdast, Feras Eid, Aleksandar Aleksov, Johanna M. Swan, Shawna M. Liff