Patents by Inventor Johanna M. Swan

Johanna M. Swan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210296175
    Abstract: Disclosed herein are methods to fabricate inorganic dies with organic interconnect layers and related structures and devices. In some embodiments, an integrated circuit (IC) structure may be formed to include an inorganic die and one or more organic interconnect layers on the inorganic die, wherein the organic interconnect layers include an organic dielectric. An example method includes forming organic interconnect layers over an inorganic interconnect substrate and forming passive components in the organic interconnect layer. The organic interconnect layers comprise a plurality of conductive metal layers through an organic dielectric material. The plurality of conductive metal layers comprises electrical pathways. the passive components are electrically coupled to the electrical pathways.
    Type: Application
    Filed: June 3, 2021
    Publication date: September 23, 2021
    Applicant: Intel Corporation
    Inventors: Aleksandar Aleksov, Feras Eid, Telesphor Kamgaing, Georgios Dogiamis, Johanna M. Swan
  • Patent number: 11095012
    Abstract: A method of forming a waveguide comprises forming an elongate waveguide core including a dielectric material; and arranging a conductive sheet around an outside surface of the dielectric core to produce a conductive layer around the waveguide core.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: August 17, 2021
    Assignee: Intel Corporation
    Inventors: Aleksandar Aleksov, Georgios C. Dogiamis, Telesphor Kamgaing, Sasha N. Oster, Adel A. Elsherbini, Shawna M. Liff, Johanna M. Swan, Brandon M. Rawlings, Richard J. Dischler
  • Publication number: 20210233856
    Abstract: Embodiments may relate to a microelectronic package that includes an overmold material, a redistribution layer (RDL) in the overmold material, and a die in the overmold material electrically coupled with the RDL on an active side of the die. The RDL is configured to provide electrical interconnection within the overmold material and includes at least one mold interconnect. The microelectronic package may also include a through-mold via (TMV) disposed in the overmold material and electrically coupled to the RDL by the mold interconnect. In some embodiments, the microelectronics package further includes a surface mount device (SMD) in the overmold material. The microelectronics package may also include a substrate having a face on which the overmold is disposed.
    Type: Application
    Filed: April 14, 2021
    Publication date: July 29, 2021
    Applicant: Intel Corporation
    Inventors: Georgios Dogiamis, Aleksandar Aleksov, Feras Eid, Telesphor Kamgaing, Johanna M. Swan
  • Patent number: 11062947
    Abstract: Disclosed herein are inorganic dies with organic interconnect layers and related structures, devices, and methods. In some embodiments, an integrated circuit (IC) structure may include an inorganic die and one or more organic interconnect layers on the inorganic die, wherein the organic interconnect layers include an organic dielectric.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: July 13, 2021
    Assignee: Intel Corporation
    Inventors: Aleksandar Aleksov, Feras Eid, Telesphor Kamgaing, Georgios Dogiamis, Johanna M. Swan
  • Publication number: 20210202403
    Abstract: Disclosed herein are structures, devices, and methods for electrostatic discharge protection (ESDP) in integrated circuits (ICs). In some embodiments, an IC component may include: a first conductive structure; a second conductive structure; and a material in contact with the first conductive structure and the second conductive structure, wherein the material has a first electrical conductivity before illumination of the material with optical radiation and a second electrical conductivity, different from the first electrical conductivity, after illumination of the material with optical radiation.
    Type: Application
    Filed: December 27, 2019
    Publication date: July 1, 2021
    Inventors: Feras Eid, Veronica Aleman Strong, Aleksandar Aleksov, Adel A. Elsherbini, Johanna M. Swan
  • Publication number: 20210202404
    Abstract: Disclosed herein are structures, devices, and methods for electrostatic discharge protection (ESDP) in integrated circuits (ICs). In some embodiments, an IC package support may include: a first conductive structure; a second conductive structure; and a material in contact with the first conductive structure and the second conductive structure, wherein the material includes a positive temperature coefficient material.
    Type: Application
    Filed: December 27, 2019
    Publication date: July 1, 2021
    Applicant: Intel Corporation
    Inventors: Feras Eid, Veronica Aleman Strong, Aleksandar Aleksov, Adel A. Elsherbini, Johanna M. Swan
  • Publication number: 20210193519
    Abstract: Disclosed herein are inorganic dies with organic interconnect layers and related structures, devices, and methods. In some embodiments, an integrated circuit (IC) structure may include an inorganic die and one or more organic interconnect layers on the inorganic die, wherein the organic interconnect layers include an organic dielectric.
    Type: Application
    Filed: December 19, 2019
    Publication date: June 24, 2021
    Applicant: INTEL CORPORATION
    Inventors: Aleksandar Aleksov, Telesphor Kamgaing, Georgios Dogiamis, Feras Eid, Johanna M. Swan, Shawna M. Liff
  • Publication number: 20210193518
    Abstract: Disclosed herein are inorganic dies with organic interconnect layers and related structures, devices, and methods. In some embodiments, an integrated circuit (IC) structure may include an inorganic die and one or more organic interconnect layers on the inorganic die, wherein the organic interconnect layers include an organic dielectric.
    Type: Application
    Filed: December 19, 2019
    Publication date: June 24, 2021
    Applicant: INTEL CORPORATION
    Inventors: Aleksandar Aleksov, Feras Eid, Telesphor Kamgaing, Georgios Dogiamis, Johanna M. Swan
  • Publication number: 20210193597
    Abstract: Embodiments may relate to a package substrate that includes a signal line and a ground line. The package substrate may further include a switch communicatively coupled with the ground line. The switch may have an open position where the switch is communicatively decoupled with the signal line, and a closed position where the switch is communicatively coupled with the signal line. Other embodiments may be described or claimed.
    Type: Application
    Filed: December 19, 2019
    Publication date: June 24, 2021
    Applicant: Intel Corporation
    Inventors: Feras Eid, Veronica Aleman Strong, Aleksandar Aleksov, Adel A. Elsherbini, Johanna M. Swan
  • Publication number: 20210193645
    Abstract: Embodiments may relate to a die with a front-end and a backend. The front-end may include a transistor. The backend may include a signal line, a conductive line, and a diode that is communicatively coupled with the signal line and the conductive line. Other embodiments may be described or claimed.
    Type: Application
    Filed: December 21, 2019
    Publication date: June 24, 2021
    Applicant: Intel Corporation
    Inventors: Aleksandar Aleksov, Adel A. Elsherbini, Feras Eid, Veronica Aleman Strong, Johanna M. Swan
  • Publication number: 20210193613
    Abstract: Embodiments of the present disclosure describe techniques for fabricating a stacked integrated circuit (IC) device. A first wafer that includes a plurality of first IC dies may be sorted to identify first known good dies of the plurality of first IC dies. The first wafer may be diced to singulate the first IC dies. A second wafer that includes a plurality of second IC dies may be sorted to identify second know good dies of the plurality of second IC dies. The first known good dies may be bonded to respective second known good dies of the second wafer. In some embodiments, the first known good dies may be thinned after bonding the first know good dies to the second wafer. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: April 1, 2016
    Publication date: June 24, 2021
    Inventors: Fay HUA, Christopher M. PELTO, Valluri R. RAO, Mark T. BOHR, Johanna M. SWAN
  • Publication number: 20210193571
    Abstract: Disclosed herein are structures, devices, and methods for electrostatic discharge protection (ESDP) in integrated circuits (ICs). In some embodiments, an IC component may include a conductive contact structure that includes a first contact element and a second contact element. The first contact element may be exposed at a face of the IC component, the first contact element may be between the face of the IC component and the second contact element, the second contact element may be spaced apart from the first contact element by a gap, and the second contact element may be in electrical contact with an electrical pathway in the IC component.
    Type: Application
    Filed: December 22, 2019
    Publication date: June 24, 2021
    Applicant: Intel Corporation
    Inventors: Adel A. Elsherbini, Feras Eid, Johanna M. Swan, Aleksandar Aleksov, Veronica Aleman Strong
  • Publication number: 20210193583
    Abstract: Various embodiments disclosed relate to a semiconductor package. The present semiconductor package includes a substrate. The substrate is formed from alternating conducting layers and dielectric layers. A first active electronic component is disposed on an external surface of the substrate, and a second active electronic component is at least partially embedded within the substrate. A first interconnect region is formed from a plurality of interconnects between the first active electronic component and the second active electronic component. Between the first active electronic component and the substrate a second interconnect region is formed from a plurality of interconnects. Additionally, a third interconnect region is formed from a plurality of interconnects between the second active electronic component and the substrate.
    Type: Application
    Filed: March 4, 2021
    Publication date: June 24, 2021
    Inventors: Adel A. ELSHERBINI, Johanna M. SWAN, Shawna M. LIFF, Henning BRAUNISCH, Krishna BHARATH, Javier SOTO GONZALEZ, Javier A. FALCON
  • Publication number: 20210193596
    Abstract: Disclosed herein are structures, devices, and methods for electrostatic discharge protection (ESDP) in integrated circuits (ICs). For example, in some embodiments, an IC package support may include: a first conductive structure in a dielectric material; a second conductive structure in the dielectric material; and a material in contact with the first conductive structure and the second conductive structure, wherein the material includes a polymer, and the material is different from the dielectric material. The material may act as a dielectric material below a trigger voltage, and as a conductive material above the trigger voltage.
    Type: Application
    Filed: December 19, 2019
    Publication date: June 24, 2021
    Applicant: INTEL CORPORATION
    Inventors: Adel A. Elsherbini, Feras Eid, Johanna M. Swan, Aleksandar Aleksov, Veronica Aleman Strong
  • Publication number: 20210193644
    Abstract: Embodiments may relate to a package substrate that is to couple with the die. The package substrate may include a signal line that is communicatively coupled with the die. The package substrate may further include a conductive line. The package substrate may further include a diode communicatively coupled with the signal line and the conductive line. Other embodiments may be described or claimed.
    Type: Application
    Filed: December 21, 2019
    Publication date: June 24, 2021
    Applicant: Intel Corporation
    Inventors: Aleksandar Aleksov, Adel A. Elsherbini, Feras Eid, Veronica Aleman Strong, Johanna M. Swan
  • Publication number: 20210194966
    Abstract: Embodiments include a sensor node, an active sensor node, and a vehicle with a communication system that includes sensor nodes. The sensor node include a package substrate, a diplexer/combiner block on the package substrate, a transceiver communicatively coupled to the diplexer/combiner block, and a first mm-wave launcher coupled to the diplexer/combiner block. The sensor node may have a sensor communicatively coupled to the transceiver, the sensor is communicatively coupled to the transceiver by an electrical cable and located on the package substrate. The sensor node may include that the sensor operates at a frequency band for communicating with an electronic control unit (ECU) communicatively coupled to the sensor node. The sensor node may have a filter communicatively coupled to the diplexer/combiner block, the transceiver communicatively coupled to the filter, the filter substantially removes frequencies from RF signals other than the frequency band of the sensor.
    Type: Application
    Filed: December 30, 2017
    Publication date: June 24, 2021
    Inventors: Georgios C. DOGIAMIS, Sasha N. OSTER, Adel A. ELSHERBINI, Erich N. EWY, Johanna M. SWAN, Telesphor KAMGAING
  • Publication number: 20210193595
    Abstract: Disclosed herein are structures, devices, and methods for electrostatic discharge protection (ESDP) in integrated circuits (ICs). For example, in some embodiments, an IC package support may include: a first conductive structure in a dielectric material; a second conductive structure in the dielectric material; and a material in contact with the first conductive structure and the second conductive structure, wherein the material includes a polymer, and the material is different from the dielectric material. The material may act as a dielectric material below a trigger voltage, and as a conductive material above the trigger voltage.
    Type: Application
    Filed: December 19, 2019
    Publication date: June 24, 2021
    Applicant: INTEL CORPORATION
    Inventors: Adel A. Elsherbini, Krishna Bharath, Feras Eid, Johanna M. Swan, Aleksandar Aleksov, Veronica Aleman Strong
  • Patent number: 11037892
    Abstract: Waveguides disposed in either an interposer layer or directly in the semiconductor package substrate may be used to transfer signals between semiconductor dies coupled to the semiconductor package. For example, inter-semiconductor die communications using mm-wave carrier signals launched into waveguides specifically tuned to optimize transmission parameters of such signals. The use of such high frequencies beneficially provides for reliable transmission of modulated high data rate signals with lower losses than conductive traces and less cross-talk. The use of mm-wave waveguides provides higher data transfer rates per bump for bump-limited dies as well as beneficially providing improved signal integrity even at such higher data transfer rates. Such mm-wave waveguides may be built directly into semiconductor package layers or may be incorporated into one or more interposed layers that are physically and communicably coupled between the semiconductor dies and the semiconductor package substrate.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: June 15, 2021
    Assignee: Intel Corporation
    Inventors: Vijay K. Nair, Sasha N. Oster, Johanna M. Swan, Telesphor Kamgaing, Georgios C. Dogiamis, Adel A. Elsherbini
  • Publication number: 20210175873
    Abstract: Embodiments may relate to a die such as an acoustic wave resonator (AWR) die. The die may include a first filter and a second filter in the die body. The die may further include an electromagnetic interference (EMI) structure that surrounds at least one of the filters. Other embodiments may be described or claimed.
    Type: Application
    Filed: December 9, 2019
    Publication date: June 10, 2021
    Applicant: Intel Corporation
    Inventors: Georgios Dogiamis, Aleksandar Aleksov, Feras Eid, Telesphor Kamgaing, Johanna M. Swan
  • Patent number: 11031666
    Abstract: An apparatus comprises a waveguide including: an elongate waveguide core including a dielectric material, wherein the waveguide core includes at least one space arranged lengthwise along the waveguide core that is void of the dielectric material; and a conductive layer arranged around the waveguide core.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: June 8, 2021
    Assignee: Intel Corporation
    Inventors: Adel A. Elsherbini, Sasha N. Oster, Georgios C. Dogiamis, Telesphor Kamgaing, Shawna M. Liff, Aleksandar Aleksov, Johanna M. Swan, Brandon M. Rawlings, Richard J. Dischler