Patents by Inventor Johanna M. Swan

Johanna M. Swan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230088545
    Abstract: Disclosed herein are waveguide interconnect bridges for integrated circuit (IC) structures, as well as related methods and devices. In some embodiments, a waveguide interconnect bridge may include a waveguide material and one or more wall cavities in the waveguide material. The waveguide interconnect bridge may communicatively couple two dies in an IC package.
    Type: Application
    Filed: November 22, 2022
    Publication date: March 23, 2023
    Inventors: Georgios DOGIAMIS, Johanna M. SWAN
  • Patent number: 11605603
    Abstract: Embodiments may relate to a microelectronic package that includes a radio frequency (RF) chip coupled with a die by interconnects with a first pitch. The RF chip may further be coupled with a waveguide of a package substrate by interconnects with a second pitch that is different than the first pitch. The RF chip may facilitate conveyance of data to the waveguide as an electromagnetic signal with a frequency greater than approximately 20 gigahertz (GHz). Other embodiments may be described or claimed.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: March 14, 2023
    Assignee: Intel Corporation
    Inventors: Adel A. Elsherbini, Georgios Dogiamis, Telesphor Kamgaing, Henning Braunisch, Johanna M. Swan, Shawna M. Liff, Aleksandar Aleksov
  • Publication number: 20230074970
    Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first microelectronic component having a first direct bonding region, wherein the first direct bonding region includes first metal contacts and a first dielectric material between adjacent ones of the first metal contacts; a second microelectronic component having a second direct bonding region, wherein the second direct bonding region includes second metal contacts and a second dielectric material between adjacent ones of the second metal contacts, wherein the first microelectronic component is coupled to the second microelectronic component by interconnects, and wherein the interconnects include individual first metal contacts coupled to respective individual second metal contacts; and a void between an individual first metal contact that is not coupled to a respective individual second metal contact, wherein the void is in the first direct bonding region.
    Type: Application
    Filed: November 9, 2022
    Publication date: March 9, 2023
    Applicant: Intel Corporation
    Inventors: Adel A. Elsherbini, Veronica Aleman Strong, Shawna M. Liff, Brandon M. Rawlings, Jagat Shakya, Johanna M. Swan, David M. Craig, Jeremy Alan Streifer, Brennen Karl Mueller
  • Publication number: 20230073026
    Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die, having a first surface and an opposing second surface, in a first layer, and including a first metallization stack at the first surface; a device layer on the first metallization stack; a second metallization stack on the device layer; and an interconnect on the first surface of the die electrically coupled to the first metallization stack; a conductive pillar in the first layer; and a second die, having a first surface and an opposing second surface, in a second layer on the first layer, wherein the first surface of the second die is coupled to the conductive pillar and to the second surface of the first die by a hybrid bonding region.
    Type: Application
    Filed: September 9, 2021
    Publication date: March 9, 2023
    Applicant: Intel Corporation
    Inventors: Adel A. Elsherbini, Kimin Jun, Shawna M. Liff, Johanna M. Swan, Han Wui Then
  • Patent number: 11600594
    Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.
    Type: Grant
    Filed: March 30, 2022
    Date of Patent: March 7, 2023
    Assignee: Intel Corporation
    Inventors: Shawna M. Liff, Adel A. Elsherbini, Johanna M. Swan, Arun Chandrasekhar
  • Patent number: 11581272
    Abstract: Embodiments may relate to a multi-chip microelectronic package that includes a first die and a second die coupled to a package substrate. The first and second dies may have respective radiative elements that are communicatively coupled with one another such that they may communicate via an electromagnetic signal with a frequency at or above approximately 20 gigahertz (GHz). Other embodiments may be described or claimed.
    Type: Grant
    Filed: April 25, 2019
    Date of Patent: February 14, 2023
    Assignee: Intel Corporation
    Inventors: Henning Braunisch, Adel A. Elsherbini, Georgios Dogiamis, Telesphor Kamgaing, Richard Dischler, Johanna M. Swan, Victor J. Prokoff
  • Patent number: 11581282
    Abstract: In embodiments, a semiconductor package may include a first die and a second die. The package may additionally include a serializer/deserializer (SerDes) die coupled with the first and the second dies. The SerDes die may be configured to serialize signals transmitted from the first die to the second die, and deserialize signals received from the second die. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: February 14, 2023
    Assignee: Intel Corporation
    Inventors: Adel A. Elsherbini, Johanna M. Swan, Shawna M. Liff, Gerald S. Pasdast
  • Patent number: 11575749
    Abstract: Embodiments include a sensor node, an active sensor node, and a vehicle with a communication system that includes sensor nodes. The sensor node include a package substrate, a diplexer/combiner block on the package substrate, a transceiver communicatively coupled to the diplexer/combiner block, and a first mm-wave launcher coupled to the diplexer/combiner block. The sensor node may have a sensor communicatively coupled to the transceiver, the sensor is communicatively coupled to the transceiver by an electrical cable and located on the package substrate. The sensor node may include that the sensor operates at a frequency band for communicating with an electronic control unit (ECU) communicatively coupled to the sensor node. The sensor node may have a filter communicatively coupled to the diplexer/combiner block, the transceiver communicatively coupled to the filter, the filter substantially removes frequencies from RF signals other than the frequency band of the sensor.
    Type: Grant
    Filed: December 30, 2017
    Date of Patent: February 7, 2023
    Assignee: Intel Corporation
    Inventors: Georgios C. Dogiamis, Sasha N. Oster, Adel A. Elsherbini, Erich N. Ewy, Johanna M. Swan, Telesphor Kamgaing
  • Patent number: 11569428
    Abstract: One superconducting qubit device package disclosed herein includes a die having a first face and an opposing second face, and a package substrate having a first face and an opposing second face. The die includes a quantum device including a plurality of superconducting qubits and a plurality of resonators on the first face of the die, and a plurality of conductive pathways coupled between conductive contacts at the first face of the die and associated ones of the plurality of superconducting qubits or of the plurality of resonators. The second face of the package substrate also includes conductive contacts. The device package further includes first level interconnects disposed between the first face of the die and the second face of the package substrate, coupling the conductive contacts at the first face of the die with associated conductive contacts at the second face of the package substrate.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: January 31, 2023
    Inventors: Jeanette M. Roberts, Adel A. Elsherbini, Shawna Liff, Johanna M. Swan, Roman Caudillo, Zachary R. Yoscovits, Nicole K. Thomas, Ravi Pillarisetty, Hubert C. George, James S. Clarke
  • Publication number: 20230016326
    Abstract: A multi-chip package includes a substrate (110) having a first side (111), an opposing second side (112), and a third side (213) that extends from the first side to the second side, a first die (120) attached to the first side of the substrate and a second die (130) attached to the first side of the substrate, and a bridge (140) adjacent to the third side of the substrate and attached to the first die and to the second die. No portion of the substrate is underneath the bridge. The bridge creates a connection between the first die and the second die. Alternatively, the bridge may be disposed in a cavity (615, 915) in the substrate or between the substrate and a die layer (750). The bridge may constitute an active die and may be attached to the substrate using wirebonds (241, 841, 1141, 1541).
    Type: Application
    Filed: September 29, 2022
    Publication date: January 19, 2023
    Inventors: Henning M. Braunisch, Chia-Pin Chiu, Aleksander Aleksov, Hinmeng AU, Stefanie M. LOTZ, Johanna M. Swan, Sujit Sharan
  • Publication number: 20230018902
    Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate, a first die coupled to the package substrate with first interconnects, and a second die coupled to the first die with second interconnects, wherein the second die is coupled to the package substrate with third interconnects, a communication network is at least partially included in the first die and at least partially included in the second die, and the communication network includes a communication pathway between the first die and the second die.
    Type: Application
    Filed: September 29, 2022
    Publication date: January 19, 2023
    Applicant: Intel Corporation
    Inventors: Adel A. Elsherbini, Amr Elshazly, Arun Chandrasekhar, Shawna M. Liff, Johanna M. Swan
  • Publication number: 20220415839
    Abstract: Embodiments disclosed herein include semiconductor dies with hybrid bonding layers and multi-die modules that are coupled together by hybrid bonding layers. In an embodiment, a semiconductor die comprises a die substrate, a pad layer over the die substrate, where the pad layer comprises first pads with a first dimension and a first pitch and second pads with a second dimension and a second pitch. In an embodiment, the semiconductor die further comprises a hybrid bonding layer over the pad layer. In an embodiment, the hybrid bonding layer comprises a dielectric layer, and an array of hybrid bonding pads in the dielectric layer, wherein the hybrid bonding pads comprise a third dimension and a third pitch.
    Type: Application
    Filed: June 24, 2021
    Publication date: December 29, 2022
    Inventors: Aleksandar ALEKSOV, Feras EID, Johanna M. SWAN, Adel A. ELSHERBINI, Shawna M. LIFF
  • Publication number: 20220415847
    Abstract: Embodiments disclosed herein include multi-die modules and methods of assembling multi-die modules. In an embodiment, a multi-die module comprises a first die. In an embodiment the first die comprises a first pedestal, a plateau around the first pedestal, and a stub extending up from the plateau. In an embodiment, the multi-die module further comprises a second die. In an embodiment, the second die comprises a second pedestal, where the second pedestal is attached to the first pedestal.
    Type: Application
    Filed: June 24, 2021
    Publication date: December 29, 2022
    Inventors: Feras EID, Johanna M. SWAN, Shawna M. LIFF, Adel A. ELSHERBINI, Aleksandar ALEKSOV
  • Patent number: 11538758
    Abstract: Disclosed herein are waveguide interconnect bridges for integrated circuit (IC) structures, as well as related methods and devices. In some embodiments, a waveguide interconnect bridge may include a waveguide material and one or more wall cavities in the waveguide material. The waveguide interconnect bridge may communicatively couple two dies in an IC package.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: December 27, 2022
    Assignee: Intel Corporation
    Inventors: Georgios Dogiamis, Johanna M. Swan
  • Publication number: 20220406701
    Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate having a surface; a die having a first surface and an opposing second surface; and a chiplet having a first surface and an opposing second surface, wherein the chiplet is between the surface of the package substrate and the first surface of the die, wherein the first surface of the chiplet is coupled to the surface of the package substrate and the second surface of the chiplet is coupled to the first surface of the die, and wherein the chiplet includes: a capacitor at the first surface; and an element at the second surface, wherein the element includes a switching transistor or a diode.
    Type: Application
    Filed: August 25, 2022
    Publication date: December 22, 2022
    Applicant: Intel Corporation
    Inventors: Adel A. Elsherbini, Kaladhar Radhakrishnan, Krishna Bharath, Shawna M. Liff, Johanna M. Swan
  • Publication number: 20220406698
    Abstract: Embodiments disclosed herein include electronic packages with magnetic features and methods of forming such packages. In an embodiment, a package substrate comprises a core and a conductive via through a thickness of the core. In an embodiment, a shell surrounds a perimeter of the conductive via and the shell is a magnetic material. In an embodiment, a surface of the conductive via is spaced away from the shell.
    Type: Application
    Filed: June 17, 2021
    Publication date: December 22, 2022
    Inventors: Aleksandar ALEKSOV, Neelam PRABHU GAUNKAR, Georgios C. DOGIAMIS, Telesphor KAMGAING, Veronica STRONG, Johanna M. SWAN
  • Publication number: 20220406751
    Abstract: A microelectronic assembly is provided, comprising: a first integrated circuit (IC) die at a first level, a second IC die at a second level, and a third IC die at a third level, the second level being in between the first level and the third level. A first interface between the first level and the second level is electrically coupled with high-density interconnects of a first pitch and a second interface between the second level and the third level is electrically coupled with interconnects of a second pitch. In some embodiments, at least one of the first IC die, second IC die, and third IC die comprises another microelectronic assembly. In other embodiments, at least one of the first IC die, second IC die, and third IC die comprises a semiconductor die.
    Type: Application
    Filed: June 22, 2021
    Publication date: December 22, 2022
    Applicant: Intel Corporation
    Inventors: Adel A. Elsherbini, Shawna M. Liff, Johanna M. Swan, Julien Sebot
  • Publication number: 20220407205
    Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to contactless transmission within a package that combines radiating elements with vertical transitions in the package, in particular to a waveguide within a core of the package that is surrounded by a metal ring. A radiating element on one side of the substrate core and above the waveguide surrounded by the metal ring communicates with another radiating element on the other side of the substrate core and below the waveguide surrounded by the metal ring. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: June 16, 2021
    Publication date: December 22, 2022
    Inventors: Telesphor KAMGAING, Neelam PRABHU GAUNKAR, Georgios C. DOGIAMIS, Johanna M. SWAN
  • Publication number: 20220406721
    Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to via structures and/or planar structures within a glass core of a substrate to facilitate high-speed signaling with a die coupled with the substrate. In embodiments, the substrate may be coupled with an interposer to enable high-speed signaling between a compute die (or tile) and a storage die (or tile) that may be remote to the substrate. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: June 17, 2021
    Publication date: December 22, 2022
    Inventors: Telesphor KAMGAING, Johanna M. SWAN
  • Publication number: 20220406725
    Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques related to glass interposers or substrates that may be created using a glass etching process to enable highly integrated modules. Planar structures, which may be vertical planar structures, created within the glass interposer may be used to provide shielding for conductive vias in the glass interposer, to increase the signal density within the glass substrate and to reduce cross talk. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: June 17, 2021
    Publication date: December 22, 2022
    Inventors: Telesphor KAMGAING, Veronica STRONG, Neelam PRABHU GAUNKAR, Georgios C. DOGIAMIS, Aleksandar ALEKSOV, Johanna M. SWAN