Abstract: A method of performance testing working parameters of a fluid handing structure in an immersion lithographic apparatus, the method including: placing a test substrate having an upper surface with a first portion with a resist defining the upper surface and a second portion with a material different from the resist defining the rest of the upper surface on a table in the immersion lithographic apparatus, confining liquid on a region of an upper surface of the table and/or the upper surface of the test substrate by operating the fluid handing structure using the associated working parameters, moving the table such that the region moves from the second portion to the first portion, and detecting change to and/or residue on the first portion as a result of liquid being left behind on the first portion during the moving.

Abstract: A method of performance testing working parameters of a fluid handing structure in an immersion lithographic apparatus, the method including: placing a test substrate having an upper surface with a first portion with a resist defining the upper surface and a second portion with a material different from the resist defining the rest of the upper surface on a table in the immersion lithographic apparatus, confining liquid on a region of an upper surface of the table and/or the upper surface of the test substrate by operating the fluid handing structure using the associated working parameters, moving the table such that the region moves from the second portion to the first portion, and detecting change to and/or residue on the first portion as a result of liquid being left behind on the first portion during the moving.

Abstract: A semiconductor device comprising a field effect transistor of the lateral or vertical DMOST type having a source zone of the one conductivity type, an adjoining channel region of the other conductivity type, a drain zone of the one conductivity type and a weakly doped drift region located between the drain zone and the channel region. According to the invention a second gate electrode located on the side of the drain zone and separated from the first gate electrode is disposed on the insulating layer above the channel zone behind the first gate electrode located on the side of the source zone. The length L.sub.2 of the part of the second gate electrode located above the channel zone is at least equal to that of the part of the first gate electrode located above the channel zone. As a result, a high value of the mutual conductance g.sub.m as well as good linearity can be obtained.

Abstract: A semiconductor device includes a first metallization pattern which is sunken into a portion of a first insulating layer on the semiconductor body. This first metallization pattern is sunken through only a part of the thickness of the first layer and its surface substantially coincides with that of the first layer. The first metallization pattern and first insulating layer are covered with a second insulating layer, and a second metallization pattern is provided on the second insulating layer. In order to provide contact with desired regions of the semiconductor device, the second metallization pattern extends through contact holes in the underlying second layer to provide the desired electrical connections. This configuration results in a flatter, more efficient and at the same time a more reliable multiple-layer metallization system.

Abstract: A method of manufacturing LOCOS transistors in which base doping, emitter doping and emitter metallization are provided via the same aperture. Problems at the edge of the sunken oxide are eliminated by a two-stage doping technique so that the channel stopper diffusion in the epitaxial layer may be omitted, which presents particular advantages in the manufacture of I.sup.2 L devices.