Abstract: A computer-implemented method for detecting artefacts in a medical image comprises obtaining input data associated with acquiring at least one image by a medical imaging system, applying a machine-learning model to the input data, whereby information about an image artefact in the image is determined, and providing the information about the image artefact, such as information about the presence and possible root-causes of the image artefact.

Abstract: A process for the production of a thermoplastic elastomer containing hard segments (a) of a polyester and soft segments (b) containing repeating units derived from an aliphatic carbonate, in which process a precursor thermoplastic elastomer is subjected to solid state post condensation at a temperature between 140 and 170° C. Also claimed is the thermoplastic elastomer.

Abstract: A process for the production of a thermoplastic elastomer containing hard segments (a) of a polyester and soft segments (b) containing repeating units derived from an aliphatic carbonate, in which process a precursor thermoplastic elastomer is subjected to solid state post condensation at a temperature between 140 and 170° C. Also claimed is the thermoplastic elastomer.

Abstract: A thermoplastic elastomer contains (a) hard segments of a polyester and (b) soft segments containing repeating units derived from an aliphatic carbonate, wherein the thermoplastic elastomer exhibits a melt flow index (MFI) measured at 230° C. under a load of 10 kg (MFI 230° C./10 kg) according to ISO1133 (2011) of at most 40 g/10 min. The thermoplastic elastomer is produced by subjecting a precursor of the thermoplastic elastomer to solid state post reaction processing at a temperature between 140 and 170° C. until the thermoplastic elastomer has the required MFI of at most 40 g/10 min measured at 230° C. under a load of 10 kg (MFI 230° C./10 kg) according to ISO1133 (2011).

Abstract: A process for the production of a thermoplastic elastomer containing hard segments (a) of a polyester and soft segments (b) containing repeating units derived from an aliphatic carbonate, in which process a precursor thermoplastic elastomer is subjected to solid state post condensation at a temperature between 140 and 170° C. Also claimed is the thermoplastic elastomer.

Abstract: Process for the production of a thermoplastic polymer comprising segments of a diamide, the process comprising: 1) a first step of preparing a reaction mixture comprising a diamine H2N—Y—NH2 Form. (I), and a diester of a dicarboxylic acid Form. (II) 2) a second step of heating the reaction mixture to a temperature at least 5° C. above the crystallization temperature of the diester and a least 5° C. below the melting temperature of the formed amide (formula III) in the presence of an alkaline or earth alkaline alkoxy catalyst Form. (III) wherein X and Y are the same or different and are an aliphatic group comprising 2-12 carbon atoms or an aromatic group comprising 6-20 carbon atoms, R1 and R2 are the same or different and are an aliphatic group comprising 2-15 carbon atoms and wherein R equals R1 or R2 and are the same or different.

Abstract: Process for the production of a thermoplastic polymer comprising segments of a diamide, the process comprising: 1) a first step of preparing a reaction mixture comprising a diamine H2N—Y—NH2 Form. (I), and a diester of a dicarboxylic acid Form. (II) 2) a second step of heating the reaction mixture to a temperature at least 5° C. above the crystallization temperature of the diester and a least 5° C. below the melting temperature of the formed amide (formula III) in the presence of an alkaline or earth alkaline alkoxy catalyst Form. (III) wherein X and Y are the same or different and are an aliphatic group comprising 2-12 carbon atoms or an aromatic group comprising 6-20 carbon atoms, R1 and R2 are the same or different and are an aliphatic group comprising 2-15 carbon atoms and wherein R equals R1 or R2 and are the same or different.

Abstract: A method of manufacturing a semiconductor device is set forth using anisotropic etching techniques, such as plasma etching and reactive ion etching to obtain interconnection patterns having accurately defined rims. Various different kinds of transistors can be manufacturing in the same semiconductor body using these techniques.

Abstract: An improved method of manufacturing a semiconductor device having a narrow groove or slot is provided. There are formed on a substrate a heavily n-doped first silicon layer, and oxidation-preventing layer such as silicon nitride, and a weakly doped or undoped second silicon layer. By means of a single masking step, a part of the second silicon layer is removed to exposed portions of the oxidation preventing layer, and the remaining part is partially oxidized. A particle bombardment of the exposed portions of the oxidation-preventing layer is carried out with the oxidized part of the second silicon layer being a mask. Subsequently, the oxide on the second silicon layer is removed leaving non-exposed portions of the oxidation-preventing layer, and then the exposed portions of the oxidation-preventing layer on the first silicon layer are completely etched away.

Abstract: On a layer having a stepped relief, such as a masking layer (4) having openings (5) on a substrate region, (2) a first layer (6) is provided, which, while maintaining the stepped relief, is covered by a second masking layer (8) and a convertible layer (9). By conversion of the convertible layer (9) (by means of ion implantation, oxidation, silicidation) this layer becomes selectively etchable. After removal of the non-converted parts, an intermediate mask (8) is formed with an opening in the second masking layer (8) along the edge of a depression (7). By means of the mask (8) thus obtained, grooves (11) are formed by anisotropic etching in the first layer (6) and in the subjacent substrate region (2) if required. When grooves are formed in a substrate region (2) of semiconductor material, these grooves may be filled with oxide (25) for forming insulated regions.

Abstract: For providing semiconductor zones (16, 18, 26) and contact metallization (19, 27) within an opening (9) in a self-registered manner, which opening is provided along its edge with polycrystalline connection parts (10) separated by an insulating material (15) from the metallization (19, 27), a protective layer (11) is formed which is maintained within the opening (9)until within this opening (9) the connection parts (10) are formed by anisotropic etching from a uniform layer of polycrystalline semiconductor material (10). The method is suitable for the manufacture of both bipolar transistors and field effect transistors.

Abstract: An improved method of manufacturing a semiconductor device having a narrow groove or slot is provided. There are formed on a substrate a heavily n-doped first silicon layer, an oxidation-preventing layer such as silicon nitride, and a weakly doped or undoped second silicon layer. By means of a single masking step, a part of the second silicon layer is removed, and the remaining part is partially oxidized. The exposed portion of the oxidation-preventing layer is removed without a further masking step by using the oxidized remaining parts of the second silicon layer. Subsequently, the oxide on the second silicon layer is removed. By thermal oxidation, a thin oxide layer is formed on the second silicon layer and an about ten times thicker oxide layer is formed on the first silicon layer. After the exposed oxidation-preventing layer has been etched away, the oxide on the second silicon layer is etched away entirely, and the oxide on the first silicon layer is etched away only superficially.

Abstract: In a semiconductor device, for example a SPS memory having narrow coplanar silicon electrodes, the electrodes are formed by etching grooves or slots having a width in the submicron range into a polycrystalline silicon layer with the slot width being defined by the oxidized edge of a silicon auxiliary layer. The electrodes are alternately covered by silicon oxide and by a layer comprising silicon nitride. The covered electrodes are first interconnected pairwise, whereupon they are separated from each other, and are provided with self-aligned contact windows. Thus, the very narrow electrodes can be contracted without technological problems and memory cells of very small dimensions are provided.

Abstract: A method of manufacturing a semiconductor device having narrow, coplanar, silicon electrodes which are separated from each other by grooves or slots having a width in the submicron range. The electrodes are alternatively covered by an oxide and by an oxidation-preventing layer, such as silicon nitride. According to the invention, a first and second electrode which are both covered with one of these layers, and which enclose a third electrode covered by the other of these layers, are first interconnected inside a connection region. Two of the three electrodes are separated from the connection region by etching. By selective etching, overlapping contact windows are provided on all three electrodes, and inside the contact windows etching of the groove is omitted.

Abstract: A method of manufacturing a semiconductor device, for example an SPS memory having narrow coplanar silicon electrodes. The electrodes are formed by etching grooves or slots (10) having a width in the submicron range into a polycrystalline silicon layer (3), the slot width being defined by the oxidized edge (6) of a silicon auxiliary layer (5). The electrodes are alternately covered by silicon oxide and by a layer comprising silicon nitride. According to the invention, the electrodes formed covered by silicon oxide (3B, 13B) are first interconnected pairwise, whereupon they are separated from each other in a separate etching step and are provided with self-aligned contact windows (15). Thus, the very narrow electrodes can be contacted without technological problems and memory cells of very small dimensions can be obtained.

Abstract: A method of manufacturing a field effect device is set forth where the source and drain zones have extensions of an accurately and reproducibly determined length adjoining the gate electrode. According to the present invention, an oxygen-preventing insulating layer is formed on a first silicon layer forming the gate electrode, and a second silicon layer is provided on the oxygen-preventing layer. A part of the second silicon layer is removed and the edges substantially coincide with the edges of the gate electrode to be formed. The edges of the remaining part of the second silicon layer are oxidized. Through successive maskless selective etching steps, the first silicon layer is exposed and etched away at the area of the oxidized etched portions. The extensions of the source and drain zones are implanted through the openings thus obtained.

Abstract: In a method of manufacturing a semiconductor device, ions are implanted into a layer of silicon nitride over a part of its surface, and the layer is then subjected to an etching treatment. According to the present invention, before the etching treatment takes place, but after the ion implantation, the layer is subjected to a heat treatment in which the implanted part of the layer obtains a higher resistance to etching than the non-implanted part. The heat treatment occurs at temperatures above 750.degree. C. Thus, a negative image of a patterned ion irradiation can be formed in the silicon nitride layer. As a result, the number of cases in which an etching or oxidation mask can be formed in a silicon nitride layer without using additional mask is considerably increased.

Abstract: According to the invention, at least one oxidation-preventing layer (2) is provided on the substrate region (1), while on this layer there is provided an oxidizable layer (3). The oxidizable layer (3) is removed above part of the substrate region (1). An edge portion (5) of the oxidizable layer (3) is oxidized. Subsequently, at least the uncovered part of the oxidation-preventing layer (2) is removed selectively and the exposed part of the substrate region is thermally oxidized through part of its thickness, while practically only at the area of the oxidized edge portion (5) the substrate region (1) is exposed and is etched away through at least part of its thickness in order to form a groove (8), the oxidizable layer (3) and the oxidized edge portion (5) being removed completely. The substrate region may be a mono- or polycrystalline silicon layer. The oxidizable layer may consist of for instance polycrystalline silicon and may be coated with a second oxidation-preventing layer (4).

Abstract: A semiconductor device of the "RESURF" type has a substrate region and a superimposed semiconductor layer which forms a p-n junction with the substrate region. The semiconductor layer has an island-shaped region which is depleted at least locally up to the surface at a reverse voltage applied across the p-n junction which is well below the breakdown voltage of the p-n junction. According to the invention the island-shaped part of the semiconductor layer over at least a part of its area has a doping profile in the vertical direction with at least two overlying layer portions with different average net doping concentrations and of the same or opposite conductivity type, so as to increase the current-carrying capacity of the semiconductor layer.

Abstract: A semiconductor device having a semiconductor layer 3 of a first conductivity type which is situated on a substrate region 4 of the second opposite type. Present within an island-shaped region 3A of the layer 3 are a surface-adjoining active zone 8 of the second conductivity type, for example the base zone of a bipolar transistor or the channel region of a field effect transistor, and a juxtaposed highly doped contact zone of the first conductivity type. The thickness and the doping concentration of the layer 3 are so small that the layer is depleted up to the surface 2 at a reverse voltage across the p-n junction 5 of the layer 3 and the substrate region 4 which is lower than the breakdown voltage. According to the invention, a highly doped buried layer 8 is present between the layer 3 and the substrate region 4 and extends at least below at least a portion of the active zone 8, the shortest distance between the edge of the buried layer 11 and the edge of the contact zones 9 being at least equal to(2V.sub.