Abstract: A device for deriving a clock signal from an electric signal made up of consecutive signal blocks (B.sub.i), each signal block having a first block section (EBD.sub.i) containing a first signal and a second block section (TBD.sub.i) containing a second signal. The input terminal (1) is coupled to two parallel circuits via a switch (3), one of the parallel circuits including a high-pass filter (8). The circuits have their outputs coupled to the inputs of a phase-locked loop (5) and a code-word detector (6). The output (13) of the code-word detector (6) is coupled to a control signal generator (15). The control signal generator (15) generates control signals which are applied to a control signal input (9) of the switch. During normal operation, the switch (3) defines a time window for the electric signal, so that only the first block sections are applied to the code-word detector (6) and the phase-locked loop (5) to derive the clock signal from the signal information in these first block sections.

Abstract: An apparatus for reproducing a pulse-code-modulated signal comprises error-correction means (3) for correcting errors in one or more of the data words forming the pcm signal. When the error-correction means are no longer capable of correcting errors in the pcm signal, they produce error flags on an output (7), which error flags are applied to a control unit (9). From these error flags the control unit (9) derives a control signal which is applied to a muting unit (6) for switching on the muting unit.A method is described by means of which the control unit derives the control signal from the error flags applied to its input (8). A first auxiliary signal (S.sub.1) is generated if (at least) n.sub.1 error flags are detected within a first time interval (T.sub.1). Subsequently, an i-th auxiliary signal (S.sub.1) is generated if (at least) n.sub.i error flags are detected within an i-th time interval (T.sub.i) which occurs after the instant at which the (i-1)-th auxiliary signal appears.

Abstract: The device comprises an input terminal (1) for receiving an electric signal and an output terminal (2) for supplying the binary digital signal. The input terminal (1) is coupled to the output terminal (2) via an equalizing unit (3) and a limiter circuit (7). The output (5) of the equalizing unit (3) is coupled to a first point of constant potential (16) via a clipper circuit (20). The output (8) of the limiter circuit (7) is coupled to the input (6) via an impedance (23). Further, the input (6) is coupled to a second point of constant potential (earth) via an integrating element (24). FIG. 1.