Abstract: Bit-serial compression process improved by inclusion of character-repeat (character) mode. During the compression process in a bit serial (bit) mode, using a predictive scheme with code words for each predicted bit, the characters, typically bytes (eight bits), are assembled bit by bit. Each assembled character is compared to the preceding character. When two successive identical characters occur, the process changes to the repeat-character mode wherein successive identical characters are signaled in the same manner as correctly predicted bits. When a different character occurs, the process signals in a manner corresponding to an incorrectly predicted bit. Provisions are made for limitations imposed by finite code spaces, for supplying a data bit when recording a code word associated with an exhausted code space or different characted, and for indicating an identical character has occurred when recording a code word associated with an exhausted code space.

Abstract: Cascaded programmable logic arrays are used to program any type of flip-flop. The latch itself can be embedded in the array when using cascaded PLA's. The arrays can be cascaded to provide logic functions using less total area than a single array embodying the same function.