Abstract: A semiconductor device comprising a memory cell, which memory cell comprises: a write transistor (TWR) a read transistor (TRE), a sense transistor (TSE) provided with a sense transistor gate, a first sense transistor electrode (7) and a second sense transistor electrode (3), the first sense transistor electrode (7) being connected to a read transistor electrode (9), the sense transistor gate being arranged as a floating gate (FG), said floating gate being separated from the second sense electrode (3) by a sense transistor oxide layer (THINOX) and from a write transistor electrode (1) by a tunnel oxide layer (TUNOX); a voltage source arrangement (5, Vsi_p, Vsi_e) to provide the second sense transistor electrode (3) with a predetermined voltage during programming and erasing, such that no stress induced leakage current occurs in the sense transistor oxide layer (THINOX).

Abstract: A semiconductor device comprising an EEPROM and a FLASH-EPROM memory is described. The EEPROM memory comprises a matrix of memory cells (ME) with a selection transistor (T2) having a selection gate (3) and arranged in series with a memory transistor (T1) having a floating gate (1) and a control gate (2). The selection transistor is also connected to a bit line (BL) and the memory transistor is also connected to a common source line (SO) of the EEPROM memory. The FLASH-EPROM memory comprises a matrix of memory cells (MF) with a memory transistor (T3) having a floating gate (4) and a control gate (5). The memory cells of the FLASH-EPROM memory also comprise a transistor (T4) having a control gate (6) connected in series with the memory cell. The memory transistor is also connected to a bit line, and the transistor, which is connected in series with the memory transistor, is also connected to a common source line (SO) of the FLASH-EPROM memory.