Abstract: A dry extract of organic humified material for cosmetic, medical or dietary use, wherein the dry extract comprises fulvic acid and humic acid, and is characterized by a maximum average particle size of 20 micrometer.

Abstract: The invention relates to an input circuit arrangement (11), which is designed for operation either in a first or a second operating mode (A, B) and comprises a connection (13) for supplying a connection signal (SWI) and a detection circuit (14). The detection circuit (14) is coupled on the input side to the connection (13) and is designed to put the input circuit arrangement (11) into an operating mode from a group comprising the first and second operating modes (A, B) depending on the steepness of a change of the connection signal (SWI).

Abstract: The invention relates to a method for installing a profiled sealing section, a profiled edge protection section or similar profiled extruded section formed of an extruded material on a component of a motor vehicle, in which the extruded material (10) is wound off a reel, at least one length section having a predefined length of the extruded material is cut off the extruded material as the profiled sealing section, profiled edge protection section or similar profiled extruded section to be installed, and is installed on the component. Prior to being wound onto the reel, the extruded material (10) is prepared such that the extruded material (10) comprises defect-free usage sections (14) having a predefined usage length (16), between which intermediate sections (18) having a predefined intermediate length (20) are arranged. As part of the installation, the intermediate sections (18) are removed from the extruded material (10) and separated as scrap.

Abstract: A circuit arrangement including a fuse comprises a fuse path (SP) which is coupled to a control input (SE) and comprises the fuse (RS) and a first charge reservoir (C1) serially connected thereto for providing a first charge state (L1), a reference path (RP) which is coupled to the control input (SE) and comprises a comparison element (RV) and a second charge reservoir (C2) serially connected thereto for providing a second charge state (L2), and an evaluation unit (AE) comprising a first input (E1) connected to the fuse path (SP) in a switchable manner, a second input (E2) connected to the reference path (RP) in a switchable manner, and a data output (DA) for providing a condition of the fuse (RS) depending on a difference between the first and second charge states (L1, L2). Further, a method for determining the condition of a fuse is provided.

Abstract: A circuit arrangement comprises a memory cell array (2) with at least one memory circuit (99). The memory circuit (99) comprises one non-volatile memory cell (98) inserted in a first current path (106) between a supply voltage terminal (9) and a reference potential terminal (8), and a volatile memory cell (97) inserted in a second current path (107) between the supply voltage terminal (9) and the reference potential terminal (8). The volatile memory cell (97) is coupled to the non-volatile memory cell (98) for reading the non-volatile memory cell (98).

Abstract: A circuit arrangement for operating voltage detection has a detection block (1) and a control block (2). Detection block (1) has a first transistor (P1) that is connected between a first supply voltage terminal (VDD) and a first node (K1) and has a first control terminal (S1), a first resistor element (R1) that is connected between first node (K1) and second supply voltage terminal (VSS), a second transistor (P2) that is connected between first supply voltage terminal (VDD) and a second node (K2) and has a second control terminal (S2), a second resistor element (R2) that is connected between second node (K2) and second supply voltage terminal (VSS), a first switch (N1) that connects first node (K1) to second control terminal (S2), and a third resistor element (R3) that is connected between second control terminal (S2) and first supply voltage terminal (VDD).

Abstract: In one embodiment, a readout circuit for rewritable memories comprises a control logic unit with an input for supplying a start signal and with several outputs for providing a respective control signal as a function of start signal, a first terminal for switchable connection to a first memory cell by means of a first switch, and a second terminal for switchable connection by means of a second switch to a second memory cell, and a readout unit coupled to the control logic unit, as well as to the first and second terminals, with an output for providing an output signal as a function of a state of the first and/or the second memory cell and as a function of the control signals, wherein the readout circuit is designed for self-terminating operation in a reading mode and in a test mode. A readout method for rewritable memories is additionally provided.

Abstract: The circuit arrangement comprises a symmetrically constructed comparator (3), a non-volatile memory cell (10) and a reference element (20). The comparator (3) exhibits a latching function, and is connected in a differential current path that joins the power supply terminal (9) to a reference potential terminal (8). The non-volatile memory cell (10) is connected in a first branch (35) of the differential current path, and the reference element (20) is connected in a second branch (55) of the differential current path.

Abstract: A circuit arrangement for operating voltage detection has a detection block (1) and a control block (2). Detection block (1) has a first transistor (P1) that is connected between a first supply voltage terminal (VDD) and a first node (K1) and has a first control terminal (S1), a first resistor element (R1) that is connected between first node (K1) and second supply voltage terminal (VSS), a second transistor (P2) that is connected between first supply voltage terminal (VDD) and a second node (K2) and has a second control terminal (S2), a second resistor element (R2) that is connected between second node (K2) and second supply voltage terminal (VSS), a first switch (N1) that connects first node (K1) to second control terminal (S2), and a third resistor element (R3) that is connected between second control terminal (S2) and first supply voltage terminal (VDD).

Abstract: In one embodiment, a readout circuit for rewritable memories comprises a control logic unit with an input for supplying a start signal and with several outputs for providing a respective control signal as a function of start signal, a first terminal for switchable connection to a first memory cell by means of a first switch, and a second terminal for switchable connection by means of a second switch to a second memory cell, and a readout unit coupled to the control logic unit, as well as to the first and second terminals, with an output for providing an output signal as a function of a state of the first and/or the second memory cell and as a function of the control signals, wherein the readout circuit is designed for self-terminating operation in a reading mode and in a test mode. A readout method for rewritable memories is additionally provided.

Abstract: A circuit arrangement including a fuse comprises a fuse path (SP) which is coupled to a control input (SE) and comprises the fuse (RS) and a first charge reservoir (C1) serially connected thereto for providing a first charge state (L1), a reference path (RP) which is coupled to the control input (SE) and comprises a comparison element (RV) and a second charge reservoir (C2) serially connected thereto for providing a second charge state (L2), and an evaluation unit (AE) comprising a first input (E1) connected to the fuse path (SP) in a switchable manner, a second input (E2) connected to the reference path (RP) in a switchable manner, and a data output (DA) for providing a condition of the fuse (RS) depending on a difference between the first and second charge states (L1, L2). Further, a method for determining the condition of a fuse is provided.

Abstract: A circuit arrangement comprises a memory cell array (2) with at least one memory circuit (99). The memory circuit (99) comprises one non-volatile memory cell (98) inserted in a first current path (106) between a supply voltage terminal (9) and a reference potential terminal (8), and a volatile memory cell (97) inserted in a second current path (107) between the supply voltage terminal (9) and the reference potential terminal (8). The volatile memory cell (97) is coupled to the non-volatile memory cell (98) for reading the non-volatile memory cell (98).

Abstract: The circuit arrangement comprises a symmetrically constructed comparator (3), a non-volatile memory cell (10) and a reference element (20). The comparator (3) exhibits a latching function, and is connected in a differential current path that joins the power supply terminal (9) to a reference potential terminal (8). The non-volatile memory cell (10) is connected in a first branch (35) of the differential current path, and the reference element (20) is connected in a second branch (55) of the differential current path.

Abstract: A melamine-formaldehyde resin solution having a formaldehyde/melamine ratio smaller than or equal to 1.5, at which it possesses a water compatibility ranging from 0.15 to 4.0 at 20° C., and a stability of at least 5 hours at a F/M ratio of 1.0, a stability of at least 6 hours at a F/M ratio of 1.1, a stability of at least 13 hours at a F/M ratio of 1.2, a stability of at least 24 hours at a F/M ratio of 1.3, a stability of at least 50 hours at a F/M ratio of 1.4, and a stability of at least 200 hours at a F/M ratio of 1.5, the stability of the resin solution being linearly dependent, within the range boundaries 1.0<F/M<1.1, 1.1<F/M<1.2, 1.2<F/M<1.3, 1.3<F/M<1.4, 1.4<F/M<1.5, upon the stabilities of the corresponding F/M range boundaries.

Abstract: The invention relates to a method and a device for producing melamine by means of the thermal conversion of urea. The invention is characterized in that: a) urea is reacted to form melamine at least partially under reaction conditions wherein an educt, an intermediate and/or an end product are present in a supercritical state; and b) the mixture consisting of at least one educt, an intermediate and/or an end product essentially forms a homogeneous phase and all educts, intermediates, and/or end products are in a complete solution. The single-phase reaction results in an especially efficient reaction.

Abstract: The invention relates to a method and a device for producing melamine by means of the thermal conversion of urea. The invention is characterized in that: a) urea is reacted to form melamine at least partially under reaction conditions wherein an educt, an intermediate and/or an end product are present in a supercritical state; and b) the mixture consisting of at least one educt, an intermediate and/or an end product essentially forms a homogeneous phase and all educts, intermediates, and/or end products are in a complete solution. The single-phase reaction results in an especially efficient reaction.