Abstract: An RF divider directly synthesizes a desired RF as a digital pattern that can be programmed and output at a VCO frequency. An exemplary RF divider comprises a pre-sequencer and a parallel-to-serial converter. The pre-sequencer successively outputs consecutive M-bit sections of a parallel word, where the parallel word comprises one or more copies of a frequency dividing bit pattern defining a frequency divisor. The parallel-to-serial converter performs a parallel-to-serial conversion on the M-bit sections of the parallel word based on the fixed radio frequency to generate an output signal having the desired radio frequency, where the output signal comprises a serial bit stream of the parallel word.

Abstract: A symmetrical, balanced, down-conversion mixer is achieved by the coordinated layout of a balanced Local Oscillator (LO) divider circuit and a balanced Radio Frequency (RF) mixer circuit, such that the LO divider is in the center and the RF mixer is arrayed symmetrically around the LO divider. In particular, the LO divider is partitioned into four portions (e.g., Ip, In, Qp, Qn), which are placed in respective quadrants, defined by orthogonal reference axes through the LO divider center. The RF mixer is similarly partitioned into four corresponding portions, which are placed around the LO divider portions in each quadrant. By integrating the LO divider and RF mixer in the layout of the symmetric, balanced, down-conversion mixer, greater component matching and control of current paths are possible, improving operational quality parameters such as IRR, IP2, and LO feedthrough.

Abstract: An RF divider directly synthesizes a desired RF as a digital pattern that can be programmed and output at a VCO frequency. An exemplary RF divider comprises a pre-sequencer and a parallel-to-serial converter. The pre-sequencer successively outputs consecutive M-bit sections of a parallel word, where the parallel word comprises one or more copies of a frequency dividing bit pattern defining a frequency divisor. The parallel-to-serial converter performs a parallel-to-serial conversion on the M-bit sections of the parallel word based on the fixed radio frequency to generate an output signal having the desired radio frequency, where the output signal comprises a serial bit stream of the parallel word.

Abstract: Disclosed is a frame synchronizing device and method for a binary data transmission system wherein digital data are transmitted as a serial bit stream organized into frames, each frame including a pre-defined frameheader, wherein said serial bit stream is inputted into a serial input portion of a serial input parallel output shift register means having at least as many stages as the number of bits of a frame, and said frames are outputted in a consecutive order from a parallel output portion of said shift register means. The particularity of the present invention is that it is detected whether or not a frameheader is present in the output of said parallel output portion, and, if not, the outputting of a frame from said parallel output portion is delayed by at least one time period which is needed for shifting a bit in said serial input portion from a stage to a next one, until synchronization is reached.