Patents by Inventor Johannes G. Ransijn
Johannes G. Ransijn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11811568Abstract: Front-end circuitry for a data receiver and related systems, methods, and devices are disclosed. The front-end circuitry includes a passive equalizer, which includes a signal input, an equalizer output including a first equalizer output and a second equalizer output, a first signal path, and a second signal path. The first signal path is between the signal input and the first equalizer output. The first signal path has a first frequency response. The second signal path is between the signal input and the second equalizer output. The second signal path has a second frequency response. The second frequency response exhibits substantially inverse behavior to that of the first frequency response. An amplifier circuit is configured to combine a first equalizer output signal from the first equalizer output with a second equalizer output signal from the second equalizer output to obtain an equalized output signal.Type: GrantFiled: August 8, 2022Date of Patent: November 7, 2023Assignee: Microchip Technology, Inc.Inventor: Johannes G. Ransijn
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Patent number: 11621872Abstract: Decision feedback equalization (DFE) tap systems and related apparatuses and methods are disclosed. An apparatus includes output nodes to provide output signals, a complementary metal-oxide-semiconductor (CMOS) DFE tap electrically connected to the output nodes, and a current integrating summer electrically connected to the output nodes. The current integrating summer is to reset the output nodes to a common mode voltage potential.Type: GrantFiled: November 18, 2021Date of Patent: April 4, 2023Assignee: Microchip Technology IncorporatedInventors: Johannes G. Ransijn, Ravish Soni
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Publication number: 20220385504Abstract: Front-end circuitry for a data receiver and related systems, methods, and devices are disclosed. The front-end circuitry includes a passive equalizer, which includes a signal input, an equalizer output including a first equalizer output and a second equalizer output, a first signal path, and a second signal path. The first signal path is between the signal input and the first equalizer output. The first signal path has a first frequency response. The second signal path is between the signal input and the second equalizer output. The second signal path has a second frequency response. The second frequency response exhibits substantially inverse behavior to that of the first frequency response. An amplifier circuit is configured to combine a first equalizer output signal from the first equalizer output with a second equalizer output signal from the second equalizer output to obtain an equalized output signal.Type: ApplicationFiled: August 8, 2022Publication date: December 1, 2022Inventor: Johannes G. Ransijn
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Patent number: 11411783Abstract: Front-end circuitry for a data receiver and related systems, methods, and devices are disclosed. The front-end circuitry includes a passive equalizer, which includes a signal input, an equalizer output including a first equalizer output and a second equalizer output, a first signal path, and a second signal path. The first signal path is between the signal input and the first equalizer output. The first signal path has a first frequency response. The second signal path is between the signal input and the second equalizer output. The second signal path has a second frequency response. The second frequency response exhibits substantially inverse behavior to that of the first frequency response. An amplifier circuit is configured to combine a first equalizer output signal from the first equalizer output with a second equalizer output signal from the second equalizer output to obtain an equalized output signal.Type: GrantFiled: December 1, 2020Date of Patent: August 9, 2022Assignee: Microchip Technology IncorporatedInventor: Johannes G Ransijn
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Publication number: 20220158875Abstract: Decision feedback equalization (DFE) tap systems and related apparatuses and methods are disclosed. An apparatus includes output nodes to provide output signals, a complementary metal-oxide-semiconductor (CMOS) DFE tap electrically connected to the output nodes, and a current integrating summer electrically connected to the output nodes. The current integrating summer is to reset the output nodes to a common mode voltage potential.Type: ApplicationFiled: November 18, 2021Publication date: May 19, 2022Inventors: Johannes G. Ransijn, Ravish Soni
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Publication number: 20210367816Abstract: Front-end circuitry for a data receiver and related systems, methods, and devices are disclosed. The front-end circuitry includes a passive equalizer, which includes a signal input, an equalizer output including a first equalizer output and a second equalizer output, a first signal path, and a second signal path. The first signal path is between the signal input and the first equalizer output. The first signal path has a first frequency response. The second signal path is between the signal input and the second equalizer output. The second signal path has a second frequency response. The second frequency response exhibits substantially inverse behavior to that of the first frequency response. An amplifier circuit is configured to combine a first equalizer output signal from the first equalizer output with a second equalizer output signal from the second equalizer output to obtain an equalized output signal.Type: ApplicationFiled: December 1, 2020Publication date: November 25, 2021Inventor: Johannes G Ransijn
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Patent number: 9391451Abstract: A distributed electrostatic discharge (ESD) protection circuit is provided. At frequencies beyond 10 GHz, the parasitic capacitance of primary ESD protection voltage clamping devices, such as diodes, hampers adequate insertion and return loss, in spite of lumped inductor tuning. An ESD protection circuit according to an embodiment of the present disclosure solves the problem by distributing the diode, or voltage clamping device, capacitance among several sections of an artificial transmission line. A transmission line is provided between a single input pad and the protected circuit, with a plurality of voltage clamping sections being distributed along the transmission line. The power and ground ESD return paths are also distributed to ensure a constant current density in the voltage clamping segments, even for fast charged-device model (CDM) discharge events. By sharing the ESD return paths between differential inputs (or outputs), these return paths have no impact on differential return or insertion loss.Type: GrantFiled: April 27, 2015Date of Patent: July 12, 2016Assignee: Microsemi Storage Solutions (U.S.), Inc.Inventor: Johannes G. Ransijn
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Patent number: 9118511Abstract: A distributed Analog Finite Impulse Response (AFIR) filter circuit with n physical taps provides an output equivalent to an AFIR filter circuit with 2n?1 taps by emulating n?1 taps. An impedance mismatch, with respect to the characteristic impedance of the input and output transmission lines, is imposed at the input and output terminals to take advantage of the resulting reflective signal paths, which emulate the additional taps. This implementation results in space-savings and power-savings for on-chip implementations of the circuit. Implementations disclosed herein are advantageous in telecommunication applications that rely heavily on copper/FR4 backplanes in serial data links.Type: GrantFiled: October 9, 2013Date of Patent: August 25, 2015Assignee: PMC-Sierra US, Inc.Inventor: Johannes G. Ransijn
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Patent number: 9019669Abstract: A distributed electrostatic discharge (ESD) protection circuit is provided. At frequencies beyond 10 GHz, the parasitic capacitance of primary ESD protection voltage clamping devices, such as diodes, hampers adequate insertion and return loss, in spite of lumped inductor tuning. An ESD protection circuit according to an embodiment of the present disclosure solves the problem by distributing the diode, or voltage clamping device, capacitance among several sections of an artificial transmission line. The power and ground ESD return paths are also distributed to ensure a constant current density in the voltage clamping segments, even for fast charged-device model (CDM) discharge events. By sharing the ESD return paths between differential inputs (or outputs), these return paths have no impact on differential return or insertion loss.Type: GrantFiled: December 19, 2012Date of Patent: April 28, 2015Assignee: PMC-Sierra US, Inc.Inventor: Johannes G. Ransijn
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Patent number: 8867182Abstract: The invention provides a signal-powered integrated circuit (IC). The IC comprises an integrated circuit die including a ground node, a supply node, and a first terminal for receiving a digital data signal having data content and a predetermined energy. A receive buffer formed on the integrated circuit die is connected to the first terminal and capable of receiving the data content associated with the digital data signal. A rectifier is also formed on the integrated circuit die. The rectifier includes a first diode connected between the first terminal and the ground node and a second diode connected between the first terminal and the supply node. The rectifier is configured to rectify the digital data signal and pass at least a portion of the digital data signal's predetermined energy to the supply node. Each of the first and second diodes is capable of withstanding an ESD impulse.Type: GrantFiled: June 7, 2010Date of Patent: October 21, 2014Assignee: Agere Systems Inc.Inventors: Boris A. Bark, Brad L. Grande, Peter Kiss, Johannes G. Ransijn, James D. Yoder
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Patent number: 8761236Abstract: The invention provides a communication protocol and serial interface having an approximately fixed interface clock and capable of accommodating a variety of communication rates. The interface employs a variable-length frame that may be expanded or reduced to obtain a desired communication rate, even though the interface clock rate is held approximately constant. The invention further provides a method for designing an agile barrier interface. In particular, the barrier clock rate is preferably selected to be an approximate common multiple of the various communication rates that the barrier interface must handle. The frame length corresponding to each communication rate may then be obtained by dividing the barrier clock rate by the ?? rate. Finally, the invention provides an agile barrier capable of communicating data across a serial interface at a variety of data rates and at an approximately fixed interface clock rate.Type: GrantFiled: April 12, 2012Date of Patent: June 24, 2014Assignee: Agere Systems LLCInventors: King-Hon Lau, Johannes G. Ransijn, Harold T. Simmonds, James D. Yoder
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Publication number: 20130251140Abstract: The invention provides a single digital communication link between system-side and line-side circuitry in a DAA, capable both of carrying data signals and of transferring a substantial amount of power to the line-side circuitry. The invention comprises a system-side interface circuit, a line-side interface circuit, and an isolation barrier including a transformer. Each interface circuit is capable of connection to an upstream communication circuit (either line-side or system-side), from which it may receive data signals to be transmitted across the isolation barrier to the other interface circuit, and to which it may pass data signals received across the isolation barrier from the other interface circuit. The line-side interface circuit may further include a rectifier and a storage device.Type: ApplicationFiled: May 10, 2013Publication date: September 26, 2013Applicant: Agere Systems LLCInventors: Johannes G. Ransijn, Boris A. Bark, James D. Yoder, Peter Kiss
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Patent number: 8442212Abstract: The invention provides a single digital communication link between system-side and line-side circuitry in a DAA, capable both of carrying data signals and of transferring a substantial amount of power to the line-side circuitry. The invention comprises a system-side interface circuit, a line-side interface circuit, and an isolation barrier including a transformer. Each interface circuit is capable of connection to an upstream communication circuit (either line-side or system-side), from which it may receive data signals to be transmitted across the isolation barrier to the other interface circuit, and to which it may pass data signals received across the isolation barrier from the other interface circuit. The line-side interface circuit may further include a rectifier and a storage device.Type: GrantFiled: April 28, 2011Date of Patent: May 14, 2013Assignee: Agere Systems LLCInventors: Johannes G. Ransijn, Boris A. Bark, James D. Yoder, Peter Kiss
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Publication number: 20120195354Abstract: The invention provides a communication protocol and serial interface having an approximately fixed interface clock and capable of accommodating a variety of communication rates. The interface employs a variable-length frame that may be expanded or reduced to obtain a desired communication rate, even though the interface clock rate is held approximately constant. The invention further provides a method for designing an agile barrier interface. In particular, the barrier clock rate is preferably selected to be an approximate common multiple of the various communication rates that the barrier interface must handle. The frame length corresponding to each communication rate may then be obtained by dividing the barrier clock rate by the EA rate. Finally, the invention provides an agile barrier capable of communicating data across a serial interface at a variety of data rates and at an approximately fixed interface clock rate.Type: ApplicationFiled: April 12, 2012Publication date: August 2, 2012Applicant: Agere Systems Inc.Inventors: King-Hon Lau, Johannes G. Ransijn, Harold T. Simmonds, James D. Yoder
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Patent number: 8213489Abstract: The invention provides a communication protocol and serial interface having an approximately fixed interface clock and capable of accommodating a variety of communication rates. The interface employs a variable-length frame that may be expanded or reduced to obtain a desired communication rate, even though the interface clock rate is held approximately constant. The invention further provides a method for designing an agile barrier interface. In particular, the barrier clock rate is preferably selected to be an approximate common multiple of the various communication rates that the barrier interface must handle. The frame length corresponding to each communication rate may then be obtained by dividing the barrier clock rate by the ?? rate. Finally, the invention provides an agile barrier capable of communicating data across a serial interface at a variety of data rates and at an approximately fixed interface clock rate.Type: GrantFiled: August 17, 2005Date of Patent: July 3, 2012Assignee: Agere Systems Inc.Inventors: King-Hon Lau, Johannes G. Ransijn, Harold Thomas Simmonds, James D Yoder
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Publication number: 20110222682Abstract: The invention provides a single digital communication link between system-side and line-side circuitry in a DAA, capable both of carrying data signals and of transferring a substantial amount of power to the line-side circuitry. The invention comprises a system-side interface circuit, a line-side interface circuit, and an isolation barrier including a transformer. Each interface circuit is capable of connection to an upstream communication circuit (either line-side or system-side), from which it may receive data signals to be transmitted across the isolation barrier to the other interface circuit, and to which it may pass data signals received across the isolation barrier from the other interface circuit. The line-side interface circuit may further include a rectifier and a storage device.Type: ApplicationFiled: April 28, 2011Publication date: September 15, 2011Applicant: AGERE SYSTEMS INC.Inventors: Johannes G. Ransijn, Boris A. Bark, James D. Yoder, Peter Kiss
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Patent number: 7969335Abstract: Digital correction of multibit ADAC nonlinearities for error feedback DACs is provided. The integral nonlinearity (INL) error of the multibit ADAC is estimated (on line or off line) by a low-resolution calibration ADC (CADC) and stored in a random-access memory (RAM) table. The INL values are then used to compensate for the ADAC's distortion in the digital domain. When this compensation is combined with mismatch-shaping techniques such as DWA, the resolution requirement for CADC can be relaxed significantly. The implementation of the proposed correction circuit for error-feedback modulators is inherently simple, since the correction only needs a digital summation without any additional digital filtering.Type: GrantFiled: March 3, 2008Date of Patent: June 28, 2011Assignee: Agere Systems Inc.Inventors: Jesus Arias, Peter Kiss, Johannes G. Ransijn, James D. Yoder
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Patent number: 7940921Abstract: The invention provides a single digital communication link between system-side and line-side circuitry in a DAA, capable both of carrying data signals and of transferring a substantial amount of power to the line-side circuitry. The invention comprises a system-side interface circuit, a line-side interface circuit, and an isolation barrier including a transformer. Each interface circuit is capable of connection to an upstream communication circuit (either line-side or system-side), from which it may receive data signals to be transmitted across the isolation barrier to the other interface circuit, and to which it may pass data signals received across the isolation barrier from the other interface circuit. The line-side interface circuit may further include a rectifier and a storage device.Type: GrantFiled: June 23, 2005Date of Patent: May 10, 2011Assignee: Agere Systems Inc.Inventors: Boris A. Bark, Peter Kiss, Johannes G. Ransijn, James D. Yoder
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Publication number: 20100246695Abstract: The invention provides a signal-powered integrated circuit (IC). The IC comprises an integrated circuit die including a ground node, a supply node, and a first terminal for receiving a digital data signal having data content and a predetermined energy. A receive buffer formed on the integrated circuit die is connected to the first terminal and capable of receiving the data content associated with the digital data signal. A rectifier is also formed on the integrated circuit die. The rectifier includes a first diode connected between the first terminal and the ground node and a second diode connected between the first terminal and the supply node. The rectifier is configured to rectify the digital data signal and pass at least a portion of the digital data signal's predetermined energy to the supply node. Each of the first and second diodes is capable of withstanding an ESD impulse.Type: ApplicationFiled: June 7, 2010Publication date: September 30, 2010Applicant: AGERE SYSTEMS INC.Inventors: Boris A. Bark, Brad L. Grande, Peter Kiss, Johannes G. Ransijn, James D. Yoder
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Patent number: 7773733Abstract: The invention provides a single digital communication link between system-side and line-side circuitry in a DAA, capable both of carrying data signals and of transferring a substantial amount of power to the line-side circuitry. The invention comprises a system-side interface circuit, a line-side interface circuit, and an isolation barrier including a transformer. Each interface circuit is capable of connection to an upstream communication circuit (either line-side or system-side), from which it may receive data signals to be transmitted across the isolation barrier to the other interface circuit, and to which it may pass data signals received across the isolation barrier from the other interface circuit. The line-side interface circuit may further include a rectifier and a storage device.Type: GrantFiled: June 23, 2005Date of Patent: August 10, 2010Assignee: Agere Systems Inc.Inventors: Boris A. Bark, Brad L. Grande, Peter Kiss, Johannes G. Ransijn, James D. Yoder