Abstract: In a video signal processing circuit comprising a complementary filter circuit (3), a subtracting circuit (27) is coupled to an input (1, 5, 33, 29) and to an output (9, 13, 25) of filter (7). The output (9) of the filter (7) is coupled, via a signal path which comprises a noise suppression circuit (43), to a combining circuit (55) which is further coupled to an output (37) of the substracting circuit (27). In order to compensate for the distortion occuring in the signal path via the noise suppression circuit (43) as a result of conversions (13, 49), the distortion in the signal path from the output (9) of the filter (7) to the subtracting circuit is made equal thereto by applying the same conversions (13, 21).

Abstract: A color television signal receiver includes a circuit arrangement for demodulating an NTSC-encoded chrominance signal available as a sequence of digital values. An oscillator circuit (33), which has an accumulator (16) and a waveform converter (31) produces two sine-shaped reference signals which are applied to a demodulator circuit (2). The accumulator (16) includes a register (18) and a (first) modulo-adder (17). A phase comparator circuit (12) controlling the phase of the reference signal receives at least one demodulated signal during the occurrence of the color synchronizing signal. The sawtooth-shaped accumulator output signal is added in a second adder (26, 38) during a first switching position of a change-over switch (23, 34) to an adjustable value and is thereafter applied to the waveform converter (31).

Abstract: A movement-adaptive transversal-recursive noise suppression circuit for a television signal can be provided in a simple way with only a single control system (19) for changing from transversal to recursive filtering while maintaining optimum noise suppression. The circuit includes a first combining circuit having a first input for receiving the television signal, a delay circuit coupled to an output of the first combining circuit and a second combining circuit having a first input coupled to an output of the delay circuit and a second input coupled to the output of the first combining circuit, the output of the delay circuit being also coupled to a second input of the first combining circuit, and an output of the second combining circuit being the output of the noise suppression circuit.

Abstract: In a television circuit arrangement for field and line frequency doubling and picture part magnification (zooming), in order to obtain the frequency doubling, information is written, alternately, into two field memories (M1, M2) during a field period having line periods at a given writing speed (clock frequency fc), whereby the reading from the field memories takes place at twice the writing speed. For a picture part magnification to be carried out in a simple manner, a magnification control circuit (TG, S3, S4, S11, S12) having a clock signal change-over circuit (S3, S4) is provided, as a result of which during writing, a higher writing speed (clock frequency 2fc) than the said given writing speed (clock frequency fc) is used during a part of the field periods and of the line periods, which part is substantially inversely proportional to the ratio between the higher writing speed and the given writing speed.

Abstract: In a series-parallel-series memory circuit (3) which requires a write clock signal (at 19), a transfer clock signal (at 25) and a read clock signal (at 31), it is sufficient, because a clock signal processing circuit (23) is provided, to apply only two clock signals (to 33 and 35). Using a gate circuit (41), it is possible to obtain from one clock signal (applied to 35) additional information, which is provided by means of pulse duration variation, for adapting the time delay of the memory circuit (FIG. 1).

Abstract: In a field number conversion circuit, the mutual positions of the horizontal and vertical synchronizing signal pattern in a field of the television signal to be converted are measured by means of a measuring circuit (201) and these mutual positions are adequately transferred by means of a coupling circuit (203) to a corresponding field in the converted television signal. Reading the field memories (125, 127) used during the conversion operation is preferably effected at a clock frequency (at 53) which is not coupled to the clock frequency (at 23) used during the writing operation.

Abstract: A device is described for electronically executing a mathematical operation, being Z=KA+(1-K)B. It is also described how this device or how several of such devices can be used for the design of a number of realizations, such as a recursive filter, a digital mixer etc. The basic idea is the electronic implementation of a mathematical function for binary variables.

Abstract: A television receiving system for converting a video signal of one line standard to a video signal of another line standard. A field delay circuit is provided which separates the video signal of the one line standard into a high frequency and low frequency portion. The low frequency portion of the signal is processed to have a delay during one field different from the delay of a subsequent field. Independent processing means for the high frequency portion of the separated signal is provided. The processed high frequency and low frequency signals are combined to provide a video signal for converting to a different line standard. By processing the high frequency and low frequency portions of the video signal differently, a savings in hardware components is realized without material degradation in performance.

Abstract: A field-frequency doubling circuit for a television signal having two field memories (23, 29) may alternatively be employed as a picture memory for the television signal when it is slightly extended by providing a re-write circuit (9, 11) and an adapted output circuit (17, 47) (FIG. 1). This picture memory may be included in, for example, a noise suppression circuit or a movement detector.

Abstract: In a noise suppression circuit for a video signal the number of elements required can be reduced when a separation circuit (3) for a high-frequency and a low-frequency component is used and the noise suppression is effected in the low-frequency component by means of a comb filter (19) which, in order to realize a still further savings in components, may comprise a delay circuit having a delay (103, 105, 107) which is switchable between a field period plus half a line period and a field period minus half a line period. The noise suppression circuit is therefore particularly suitable for use in television receivers.

Abstract: In a noise suppression circuit for a video signal, the input video signal is separated into its high and low frequency components by a separating circuit (3). The signal at an output (15) of a delay circuit (17) is combined with the separated low frequency signal in a combining circuit (11) whose output is applied to the input (19) of the delay circuit (17). The time delay of the delay circuit (17) is switched from field to field by means of a change-over switch (53) so that this time delay changes from field to field to a field period minus and a field period plus half a line period. The noise-suppressed low frequency output from the combining circuit (11) is added to the separated high frequency component in an adder circuit (25). In use such a noise suppression circuit produces substantially no travelling noise patterns on a television display.