Abstract: There is disclosed a first stub short bonded across conductive runners of a tuning stub at a distance preferably greater than a distance resulting in the desired frequency of operation of a voltage controlled oscillator tuned by the tuning stub. Thereafter, the voltage controlled oscillator is powered and tested to determine the frequency of operation of the voltage controlled oscillator. The position of a second stub short is determined based on the frequency of oscillation of the oscillator due to the presence of the first stub short, the geometry of the tuning stub and the desired frequency of operation of the voltage controlled oscillator. A second stub short is precisely positioned along the stub using automated equipment, relative to the position of the first stub short, to result in the desired frequency of operation of the voltage controlled oscillator.

Abstract: A clock recovery circuit includes a sampling phase detector and frequency detector. The sample values generated in the phase detection portion of the clock recovery circuit and applied as inputs to the frequency detector to allow for frequency “cycle slips” to be detected and corrected without requiring the use of a separate circuit.

Abstract: A self-aligned clock recovery circuit for synchronizing a local clock with an input data signal includes a sampling type phase detector for generating an output signal based on the phase difference between the local clock and the data signal timing. The phase detector obtains samples of consecutive data symbols at sampling times corresponding to transitions of the local clock, and obtains a data crossover sample at a sampling instant in between those of the consecutive data symbol samples. A phase shifter is employed to phase shift the local clock by an amount corresponding to a time varying modulation signal so as to obtain each data crossover sample at a variable sampling instant relative to the associated consecutive symbol samples.

Abstract: Disclosed is a data regeneration circuit including a decision gate for regenerating a symbol stream (e.g., bit stream) by comparing the amplitude of individual symbols thereof to a decision threshold and outputting a logic level in accordance with each comparison. Threshold optimization circuitry dynamically measures first and second probability distribution points of each symbol, and based on the measurements, optimizes the decision threshold applied to the decision gate. A parallel pseudoerror path including a pseudoerror decision gate and pseudoerror counter may be employed to facilitate the measurements.

Abstract: A dynamic laser diode drive circuit is formed so that the gain of the final gain stage is controlled in association with the level of the drive current supplied to the laser diode. In particular, the current sources associated with the final gain stage and the output stage and commonly controlled so that the gain tracks the current level. That is, in situations required a relatively low current, the gain is minimized to prevent overdriving the output stage (a situation common in prior art arrangements). When a larger laser drive current is required, the gain of the final stage is adjusted to increase the output from this stage and provide a sufficient voltage differential to drive the output stage.

Abstract: A high speed logic module is formed to include a differential input formed as a pair of inductive transmission lines and a differential output also formed as a pair of inductive transmission lines. A pair of logic devices are included in the module, with the gate terminals of the devices coupled to separate ones of the input inductive transmission lines. The output terminals of the logic devices are coupled to separate ones of the pair of output inductive transmission lines. The effects of the intrinsic gate-to-drain capacitance C.sub.gd inherent in each logic device is compensated for by including a pair of cross-coupled neutralizing capacitors between the drain and gate terminals of the logic devices. Various logic circuits, such as oscillators, latches, delay lines, etc. can be formed using the differential, neutralized structure of the invention.