Abstract: A polyphase harmonic rejection mixer, comprising a plurality of stages following each other; wherein a first stage is arranged to perform at least frequency conversion; and a second stage is arranged to perform at least selective weighting and combining; wherein at least two of the plurality of stages are arranged to perform at least combining. In an embodiment, the first stage (28) comprises three single-ended gain blocks (10, 12, 14), arranged to perform selective weighting, frequency conversion and combining; and a second stage (30) following the first stage (28) and arranged to perform selective weighting and combining. The second stage (30) may reduce the number of phases output by the first stage (28) and may output (32) a complex differential down converted signal. The mixer may be directly interfaced to an antenna of an LNA-less receiver without weighting in the first stage. The mixer may be included in a software-defined radio.

Abstract: A circuit for producing multiple switching control signals for a harmonic rejection mixer from multiple phases of a digital local oscillator signal is presented, wherein a first waveform combiner circuit is arranged to generate from the multiple phases of the digital local oscillator signal at least one switching control signal by logical combining two from the multiple phases of a digital local oscillator signal, and a second waveform combiner circuit is arranged to generate from the multiple phases of the digital local oscillator signal at least one first switching control signal by logical combining one from the multiple phases of a digital local oscillator signal with a predetermined signal having a static logical value.

Abstract: There is provided a method and apparatus for maintaining a bias current that flows through two transistors at a target level. The two transistors are both connected to form a series network between positive and negative voltage supply terminals. The bias current flows through the two transistors when the circuit is at equilibrium, and the threshold voltage of the transistors is controlled by controlling the voltage that is applied to the transistors bulk terminals. In addition to the two transistors, there is provided a control circuit that measures a circuit parameter that is indicative of the level of bias current flowing through the two transistors. In response to the measured parameter, the control circuit adjusts the bulk voltage levels of the two transistors so as to alter the transistors threshold voltages and maintain the level of bias current at a target level.

Abstract: A polyphase harmonic rejection mixer, comprising a plurality of stages following each other; wherein a first stage is arranged to perform at least frequency conversion; and a second stage is arranged to perform at least selective weighting and combining; wherein at least two of the plurality of stages are arranged to perform at least combining. In an embodiment, the first stage (28) comprises three single-ended gain blocks (10, 12, 14), arranged to perform selective weighting, frequency conversion and combining; and a second stage (30) following the first stage (28) and arranged to perform selective weighting and combining. The second stage (30) may reduce the number of phases output by the first stage (28) and may output (32) a complex differential down converted signal. The mixer may be directly interfaced to an antenna of an LNA-less receiver without weighting in the first stage. The mixer may be included in a software-defined radio.

Abstract: An electronic device comprising a passive harmonic-rejection mixer. The passive harmonic rejection mixer has an input connected to several sub-mixer stages, and the sub-mixer stages are connected to a summing module for generating the output. Each sub-mixing stage comprises a gating module and a respective amplifier, the gating module adapted to selectively pass the input signal or the input signal with inverted polarity under the control of control signals.

Abstract: An antenna assembly for wireless communication equipment comprises an antenna structure comprising at least a loop type antenna arranged to deliver a first current when it is used in a balanced mode and/or a second current when it is used in an unbalanced mode with respect to a ground plane from received radio signals, and current extraction device coupled to the antenna structure and arranged to be placed in at least a first state in which the current extraction device delivers the first or second current and a second state in which the current extraction device simultaneously delivers the first and second currents either separately or mixed together.

Abstract: A circuit for producing multiple switching control signals for a harmonic rejection mixer from multiple phases of a digital local oscillator signal is presented, wherein a first waveform combiner circuit is arranged to generate from the multiple phases of the digital local oscillator signal at least one switching control signal by logical combining two from the multiple phases of a digital local oscillator signal, and a second waveform combiner circuit is arranged to generate from the multiple phases of the digital local oscillator signal at least one first switching control signal by logical combining one from the multiple phases of a digital local oscillator signal with a predetermined signal having a static logical value.

Abstract: There is provided a method and apparatus for maintaining a bias current (IBIAS1) that flows through two transistors (MN2, MP2) at a target level. The two transistors are both connected to form a series network between positive (VDD) and negative (GND) voltage supply terminals. The bias current flows through the two transistors (MN2, MP2) when the circuit is at equilibrium, and the threshold voltage of the transistors is controlled by controlling the voltage (VB1, VB2) that is applied to the transistors bulk terminals. In addition to the two transistors, there is provided a control circuit (25) that measures a circuit parameter (VDD) that is indicative of the level of bias current flowing through the two transistors. In response to the measured parameter, the control circuit adjusts the bulk voltage levels of the two transistors (VB1, VB2) SO as to alter the transistors threshold voltages and maintain the level of bias current at a target level.

Abstract: A frequency-division circuit comprises a pair of multi-state circuits (MSCA, MSCB). Each multi-state circuit can be switched throughout a cycle of states (SA(1), . . . , SA(N); SB(1), . . . , SB(N)). One multi-state circuit (MSCA) switches to a next state in response to a rising edge (Er) in an input signal (OS). The other multi-state circuit (MSCB) switches to a next state in response to a falling edge (Ef) in the input signal (OS). Each multi-state circuit (MSCA, MSCB) has at least one state (SA(1), SB(1)) in which the multi-state circuit inhibits the other multi-state circuit (MSCB, MSCA) so as to prevent the other multi-state circuit from switching to the next state.

Abstract: An antenna assembly (AA), for wireless communication equipment, comprises i) an antenna structure comprising at least a loop type antenna (LA) arranged to deliver a first current when it is used in a balanced mode and/or a second current when it is used in an unbalanced mode with respect to a ground plane (GP) from received radio signals, and E) current extraction means (A1) coupled to the antenna structure (LA) and arranged to be placed in at least a first state in which they deliver the first or second current and a second state in which they simultaneously deliver the first and second currents either separately or mixed together.

Abstract: A frequency-division circuit comprises a pair of multi-state circuits (MSCA, MSCB). Each multi-state circuit can be switched throughout a cycle of states (SA(1), . . . , SA(N); SB(1), . . . , SB(N)). One multi-state circuit (MSCA) switches to a next state in response to a rising edge (Er) in an input signal (OS). The other multi-state circuit (MSCB) switches to a next state in response to a falling edge (Ef) in the input signal (OS). Each multi-state circuit (MSCA, MSCB) has at least one state (SA(1), SB(1)) in which the multi-state circuit inhibits the other multi-state circuit (MSCB, MSCA) so as to prevent the other multi-state circuit from switching to the next state.

Abstract: A receiver having a phase-locked loop (PLL) for synchronizing its oscillator with a carrier (CA). A calibration circuit (CAL) calibrates the phase-locked loop's oscillator (OSC) in the following manner. It measures (FMC) the frequency difference (dF) between a nominal frequency (Fnom) of the carrier (CA) and a frequency (Fosc) of the phase-locked loop's oscillator (OSC). Furthermore, it adjusts the frequency (Fosc) of the PLL oscillator in accordance with the measured frequency difference (dF). As a result, the phase-locked loop's oscillator will be substantially tuned to the nominal frequency of the carrier. The actual frequency of the carrier may differ from the nominal frequency. In general, such a difference will be sufficiently small for the phase-locked loop (PLL) to capture the carrier (CA).

Abstract: A mixer oscillator stage, which can be used both with a switched 2-band concept and a 3-band concept without changing the architecture of the oscillators which exceeds the number of mixers and by coupling the mixer(s) and oscillators via a switching circuit so as to switch between the different oscillators in dependence upon the part of the band converging the signal.

Abstract: In a receiver, two tuners (TUN1,TUN2) provide concurrent reception of mutually different signals. The two tuners are merged into one module (MOD). This may give rise to mutual interference. However, there are various cost-efficient measures to counter such mutual interference. One such measure is that an oscillation frequency in either of the two tuners does not coincide with the radio frequency, or any sub-harmonic of the radio frequency, of the signal received by the respective other tuner.

Abstract: A receiver for receiving both first-type reception signals, for example TV signals, and second-type reception signals, for example, FM-radio signals. The receiver may be used in multimedia applications. In the receiver, a reception signal is fed via an input section RFI-L, RFA-L, BPF-L to a mixer MIX-L. To obtain a relatively good performance, a band-pass filter BPF-L in the input section can be tuned through a frequency band, in which reception signals of both the first and the second type are present. The filter characteristics of the band-pass filter BPF-L are switched in accordance with the type of reception signal desired. For example, switching provides a passband which is substantially narrower for FM reception than for TV reception.

Abstract: A receiver for receiving reception signals of a first type, for example, TV signals, and reception signals of a second type, for example, FM-radio signals. The receiver may be used in multimedia applications. In the receiver, a single tuner TUN frequency converts a reception signal RFS into an intermediate frequency signal IFS. For relatively small-size implementations, the receiver is a single conversion receiver for both types of reception signals, the single conversion being effected in the tuner TUN. Depending on whether a first-type or second-type reception signal is desired, the tuner TUN provides the intermediate frequency signal IFS at a first intermediate frequency IF1 or a second intermediate frequency IF2, respectively. The intermediate frequency signal IFS at intermediate frequency IF1 is processed in a first intermediate frequency signal processor IFSP1.

Abstract: A receiver for receiving reception signals of a first type, for example, TV signals, and reception signals of a second type, for example FM-radio signals, is described. The receiver may be used in multimedia applications. In the receiver, an input section TVIN,FMIN,SWIN includes at least two inputs TVIN,FMIN to which reception signals can be applied. One input TVIN may, for example, be coupled to a cable network via which reception signals are distributed. The other input FMIN may, for example, be used to plug-in a simple wire antenna. In many cases, such a wire antenna will be sufficient to receive on-air reception signals with acceptable quality. The invention takes into consideration that on-air reception signals may not always be offered by the cable network. With at least two inputs TVIN,FMIN, there is flexibility of reception.

Abstract: In a tuning system, a DC-DC converter DDC provides a tuning control voltage Vt for a tuner TUN. The DC-DC converter DDC is in the form of a series arrangement of an AC source CAC, an inductive element IND and a rectifier circuit REC. The AC signal provided by the AC source Vac1 is controlled by a tuning error signal Se from a tuning detector circuit TED. The inductive element IND transforms this AC signal Vac1 into an AC signal of higher amplitude Vac2. The latter AC signal Vac2 is rectified to provide the tuning control voltage Vt. In effect, the DC-DC converter DDC is part of a tuning control loop. This tuning control loop TUN, TED, DDC determines the output voltage of the DC-DC converter Vt.

Abstract: An arrangement for receiving both TV and FM broadcast signals, particularly suited for multi-media applications. In the arrangement, a standard TV tuner (TUN) effects a first frequency conversion of an FM broadcast signal. A combination of a mixer (MP2) and an oscillator (VCO) effects a second frequency conversion of the FM broadcast signal. In order to keep the arrangement relatively simple, the oscillator (VCO) is included in a phase-lock loop (PLL), which is used for synchronous detection of a TV intermediate frequency signal. The phase-lock loop (PLL) includes a switch (SW) for deactivating the phase-lock loop (PLL) in the case of FM broadcast signal reception, such that the oscillator (VCO) is effectively free running.

Abstract: In a television receiver having an automatic adjustment circuit for a radio frequency resonant circuit (3) of the receiver, using two carriers fed to the read frequency input of the receiver, the product of the amplitudes of the two carriers is formed by means of a detection circuit (37) coupled to an output (5) of the radio frequency circuit (3) and the adjustment setting of the resonant circuit is effected to a maximum value of this product (at 77), thus providing a simple, correct adjustment.