Abstract: An optical read/write apparatus includes a first detector for detecting light reflected from an optical record carrier and generating a signal; and a signal processing unit. The processing unit includes: a common input clamp coupled to the first detector; separation apparatus for separating low frequency and high frequency components of the detected signal, including a capacitive element; low frequency apparatus for processing the low frequency components and including a current mirror having a first output clamp and a first input clamp coupled to the common input clamp. The processor unit further includes high frequency apparatus for processing the high frequency components and including: a current source with a current output clamp; a second current mirror with an input branch; a second input clamp coupled to the common input clamp via the capacitive element; and a second output clamp.

Abstract: To enable a serial data signal to be sampled reliably through a longer time period, the data signal is applied to a data slicer with a dynamically variable slice level. The slice level is dynamically adjusted in dependence upon a feedback of the sliced signal. A track-and-hold circuit, with control feedback from a low pass filter and peak detectors, provides for a design which is tolerant of timing variations. Also disclosed are circuits for reducing the effects of cochannel and other interferences.

Abstract: An amplifier stage including a differential pair (T1, T2) is provided with a resistive ladder (R1 . . . R2n) coupled between the second control electrodes of said differential pair. Taps on mirror positions along the resistive ladder (R1 . . . R2n) are switchably connected to first and second current source transistors (T3, T4), the current source transistors having their control electrodes connected to the first main electrodes of the transistors forming the differential pair. By placing the switches in series with the current source transistors (T3, T4), the influence of the non-linear impedance of the switches is reduced to negligibly small proportions as the output impedance of the current source transistors (T3, T4) is considerably higher than the impedance of the switches. Thus, a linear conversion impedance is obtained.

Abstract: A sample-and-hold circuit comprises a first buffer stage, a first sampling switch, a sampling capacitor, and a feedback output amplifier for supplying a sampled output signal (Uout). The sampling capacitor is connected to an output of a second buffer stage, which has an input connected to earth. The output amplifier receives feedback via a third buffer stage and a second sampling switch and via a fourth buffer stage and a second sampling capacitor, which together with the first sampling switch are controlled by the same clock signal. The first sampling switch gives rise to clock feedthrough at the non-inverting input of the output amplifier. This clock feedthrough is cancelled by an equal clock feedthrough at the inverting input, so that the sampled output signal is freed from undesired clock feedthrough.

Abstract: A common-mode signal sensor for supplying a common-mode signal in response to a difference signal. A first input terminal and a second input terminal receive the difference signal and an output terminal supplies the common-mode signal. A first differential pair of a first conductivity type is connected to a first current source at a first node and has its control electrodes connected to the input terminals. A second differential pair of a second conductivity type opposite to the first conductivity type is connected to a second current source at a second node and has its control electrodes also connected to the input terminals. A diode-connected fifth transistor of the first conductivity type is connected between the first node and the output terminal and a diode-connected sixth transistor of the second conductivity type is connected between the second node and the output terminal.

Abstract: A universal signal converter composed of a first current mirror having a first input terminal adapted to receive a first input signal and a first output terminal. A first common terminal is coupled to a first reference terminal. The signal converter is adapted to receive a second input signal via the first output terminal. The converter further comprises a second current mirror having a second input terminal coupled to a second reference terminal, a second output terminal adapted to supply a first output signal, and a second common terminal coupled to the first output terminal. A third current mirror has a third input terminal coupled to the second reference terminal and a third output terminal adapted to supply a second output signal. A third common terminal is coupled to the first input terminal and a bias current source is coupled between the second and the third input terminal and the second reference terminal.