Abstract: An architecture and frequency plan for a wideband UHF radio minimizing spurious output signal emissions uses a low value for the ratio of the maximum RF operating frequency to the (first) intermediate frequency (IF) in the radio, as part of its internal superheterodyne conversion process. A minimum value or a value sufficiently close to the minimum value of this ratio allows the radio design to be optimized to reduce spurious outputs and the effects of inherently present major harmonics. These and other advantages and features permit a radio design to be realized in a cost effective manner for an array of stringent performance specifications including low spurious output emissions.

Abstract: A fast acting noise squelch control circuit for FM radio receivers samples the noise above the audio band to determine the presence of an RF carrier. The detected noise signal is integrated by a low-pass frequency gain integrating filter and compared, using a high gain differential amplifier, against a preset squelch threshold voltage to provide a signal indicative of the presence or absence of a received carrier. The output of the integrating filter is initialized at a reference voltage that is only slightly below the threshold voltage setting for the comparator to minimize integration time and increase sensitivity of the squelch. In this manner, a long time constant in the noise integrating filter can be used without having to wait for a long time to establish whether a carrier signal is present.

Abstract: An improved adaptive loop lag filter for phase locked loop frequency synthesizers used in scanning receivers includes an additional resistor controllably inserted into the lag filter by a series-coupled C-MOS switch. The filter can be operated in an intermediate bandwidth mode. Switching to an intermediate bandwidth mode from the wide bandwidth mode before switching to a narrow bandwidth mode reduces the magnitude and duration of disturbances at the VCO output during bandwidth switching and promotes rapid settling of the synthesizer. The improved filter also includes a capacitor coupled between the output of the series-coupled switch and a signal ground to further attenuate any switching transients.

Abstract: A single input wideband modulation system for a phase locked loop is achieved by interposing the inverse analogue of the closed phase locked loop transfer function between the modulation source and the VCO modulation input. A first branch of the interposed circuit directly passes high frequency signals from the modulation source to a summing device tied to an input of the VCO. A second branch of the interposed circuit boosts low frequency signals and blocks high frequency signals recieved from the modulation source and passes such signal to the summing device where signals from the first and second branches are summed to permit wideband modulation of the VCO. All the modulation processing is performed outside the phase locked loop.

Abstract: Several embodiments are disclosed of a modulation equalization network associated with a phase locked loop to achieve frequency independent modulation of the VCO. The equalization network is disposed to introduce the modulation signal into the control loop ahead of the loop filter but after the phase detector output. The interposed equalization network requires only a single input port to achieve a flat modulation response thereby lending itself to a modular implementation. The modulation processing is performed totally outside the phase locked loop. The network serves to provide a boost to low frequency signals from the modulation source using an integrator network while providing a high frequency response that is essentially the inverse of the phase locked loop filter response.

Abstract: A circuit arrangement for combining a temperature compensating signal from a temperature compensator with a modulation signal to provide a combined signal for driving one or more crystal oscillators independently. The combining is carried out in such a manner that there is a constant predetermined ratio between the magnitudes of the temperature compensating and modulating signals. A potentiometer level controls the combined signal to each oscillator independently without changing the predetermined ratio. Thus, the effect of circuit element tolerances on temperature compensation is automatically corrected for while the central oscillation frequency in the absence of modulation is substantially unaffected.

Abstract: A scanning receiver is provided with a pause detector which causes the receiver to tune to a priority channel during pauses in the transmission on a nonpriority channel. If a priority transmission is present, the receiver remains on the priority channel until the priority transmission ends. If no priority transmission is present, the receiver is tuned back to the former nonpriority channel.

Abstract: A tunable coupling network for a frequency multiplier stage providing a passband for a desired harmonic of a fundamental frequency and rejection notches for undesired harmonic frequencies. The passband of the network can be tuned by changing the value of at least one circuit element to track the desired harmonic of the fundamental frequency over a range of fundamental frequencies. In so doing, the rejection notches also move so that they maintain fixed ratios with respect to the passband frequency as the passband moves. In one embodiment the network comprises first and second tunable circuits each including a variable reactive element. The first resonant circuit includes a variable capacitor and two fixed inductors. The second resonant circuit includes a variable inductor and two fixed capacitors. The two resonant circuits are coupled by an interstage coupling capacitor.

Abstract: A phase locked loop synthesizer including a phase locked loop (PLL) having a first characteristic loop bandwidth, for generating a synthesized signal, the PLL including a signal controlled oscillator (SCO) having first and second control inputs for controlling the frequency of the SCO, the first control input receiving a signal from the PLL, and a subsidiary frequency compression loop (FCL) having a second characteristic bandwidth wider than said first characteristic bandwidth, the FCL having an output coupled to the second control input of the SCO whereby said SCO is subject to frequency control by both the PLL and the FCL.

Abstract: A phase-locked loop circuit for use in locking onto a sub-harmonic of the frequency of a reference source. An oscillator operating at the sub-harmonic frequency is injection-synchronized to the primary voltage controlled oscillator of the phase-locked loop, thereby causing it to function as a divider. The injection-synchronized oscillator can be controlled by a loop control signal generated by the loop's phase detector and loop filter.

Abstract: A voltage controlled oscillator (VCO) and reference oscillator are connected in a phase locked loop with a first phase detector, loop switch, and acquisition sawtooth sweep circuit. A second phase detector and fast integrator circuit are connected to the VCO and reference oscillator in quadrature relation with respect to the first phase detector. As the acquisition sweep circuit sweeps the VCO, the fast integrator produces a signal whose magnitude increases as the swept VCO frequency approaches the frequency needed for the phase locked loop to achieve phase lock. When this signal magnitude exceeds a predetermined threshold, an output control signal is produced. This output control signal causes the loop switch to close and make the phase locked loop operational. A delay circuit is connected to the second phase detector and fast integrator. The delay circuit produces a delayed output at a predetermined time after the control signal is produced.