Patents by Inventor Johannes Laven
Johannes Laven has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11121242Abstract: A method is provided for operating a semiconductor device which includes an IGBT having a desaturation semiconductor structure connected to a first electrode terminal and a gate electrode terminal for controlling a desaturation channel. The method includes: applying a first gate voltage to the gate electrode terminal so that current flows through the IGBT between the first electrode terminal and a second electrode terminal and current flow through the desaturation channel is substantially blocked; applying a different second gate voltage to the gate electrode terminal so that current flows through the IGBT between the first and second electrode terminals and charge carriers flow as a desaturating current through the desaturation channel to the first electrode terminal; and applying a different third gate voltage to the gate electrode terminal so that current flow through the IGBT between the first and second electrode terminals is substantially blocked.Type: GrantFiled: July 1, 2020Date of Patent: September 14, 2021Assignee: Infineon Technologies AGInventors: Johannes Laven, Hans-Joachim Schulze
-
Publication number: 20200335613Abstract: A method is provided for operating a semiconductor device which includes an IGBT having a desaturation semiconductor structure connected to a first electrode terminal and a gate electrode terminal for controlling a desaturation channel. The method includes: applying a first gate voltage to the gate electrode terminal so that current flows through the IGBT between the first electrode terminal and a second electrode terminal and current flow through the desaturation channel is substantially blocked; applying a different second gate voltage to the gate electrode terminal so that current flows through the IGBT between the first and second electrode terminals and charge carriers flow as a desaturating current through the desaturation channel to the first electrode terminal; and applying a different third gate voltage to the gate electrode terminal so that current flow through the IGBT between the first and second electrode terminals is substantially blocked.Type: ApplicationFiled: July 1, 2020Publication date: October 22, 2020Inventors: Johannes Laven, Hans-Joachim Schulze
-
Patent number: 10529838Abstract: A semiconductor device includes at least one transistor structure. The at least one transistor structure includes an emitter or source terminal, and a collector or drain terminal. A carbon concentration within a semiconductor substrate region located between the emitter or source terminal and the collector or drain terminal varies between the emitter or source terminal and the collector or drain terminal.Type: GrantFiled: December 4, 2017Date of Patent: January 7, 2020Assignee: Infineon Technologies AGInventors: Hans-Joachim Schulze, Moriz Jelinek, Johannes Laven, Helmut Oefner, Werner Schustereder
-
Patent number: 10312258Abstract: A semiconductor device includes a semiconductor substrate with a first surface. The device further includes one or more semiconductor devices formed or the first surface in an active area. The device further includes a plurality of cavities in the semiconductor substrate beneath the first surface. The device further includes dielectric support structures between each of the cavities and spaced apart from the first surface. The dielectric support structures support a part of the semiconductor substrate between the active area and the cavities. The dielectric support structures include an oxide.Type: GrantFiled: July 13, 2016Date of Patent: June 4, 2019Assignee: Infineon Technologies AGInventors: Johannes Laven, Matteo Dainese, Hans-Joachim Schulze
-
Patent number: 9972689Abstract: According to one embodiment of a semiconductor device, the semiconductor device includes a semiconductor substrate having a first surface, an insulation layer having a laterally varying thickness on the first surface, and a metal layer on the first surface. The insulation layer has ripples in its surface facing the metal layer. According to another embodiment of a semiconductor device, the semiconductor device includes a semiconductor substrate having a first surface and including at least one of a laterally varying thickness and an inclined first surface. The first surface of the semiconductor substrate has ripples.Type: GrantFiled: October 23, 2014Date of Patent: May 15, 2018Assignee: Infineon Technologies AGInventors: Hans-Joachim Schulze, Johannes Laven, Holger Schulze
-
Publication number: 20180102423Abstract: A semiconductor device includes at least one transistor structure. The at least one transistor structure includes an emitter or source terminal, and a collector or drain terminal. A carbon concentration within a semiconductor substrate region located between the emitter or source terminal and the collector or drain terminal varies between the emitter or source terminal and the collector or drain terminal.Type: ApplicationFiled: December 4, 2017Publication date: April 12, 2018Inventors: Hans-Joachim Schulze, Moriz Jelinek, Johannes Laven, Helmut Oefner, Werner Schustereder
-
Patent number: 9917186Abstract: A semiconductor device includes transistor cells and control structures. The transistor cells include source zones of a first conductivity type and body zones of a second conductivity type. The source and body zones are formed in a semiconductor mesa formed from a portion of a semiconductor body. The control structures include first portions extending from a first surface into the semiconductor body on at least two opposing sides of the semiconductor mesa, second portions between the first portions and separated from the first surface by portions of the semiconductor mesa, and third portions connecting the first and the second portions and separated from the first surface by portions of the semiconductor mesa. Constricted sections of the semiconductor mesa separate third portions neighboring each other along a horizontal longitudinal extension of the semiconductor mesa.Type: GrantFiled: December 29, 2016Date of Patent: March 13, 2018Assignee: Infineon Technologies AGInventors: Johannes Laven, Hans-Joachim Schulze, Matteo Dainese, Peter Lechner, Roman Baburske
-
Patent number: 9847229Abstract: A method for forming a semiconductor device includes depositing an epitaxial layer on a semiconductor substrate, forming an oxygen diffusion region within the epitaxial layer by oxygen diffusion from the semiconductor substrate into a part of the epitaxial layer and tempering at least the oxygen diffusion region of the epitaxial layer at a temperature between 400° C. and 480° C. for more than 15 minutes.Type: GrantFiled: May 7, 2015Date of Patent: December 19, 2017Assignee: Infineon Technologies AGInventors: Hans-Joachim Schulze, Johannes Laven
-
Patent number: 9754787Abstract: A Magnetic Czochralski semiconductor wafer having opposing first and second sides arranged distant from one another in a first vertical direction is treated by implanting first particles into the semiconductor wafer via the second side to form crystal defects in the semiconductor wafer. The crystal defects have a maximum defect concentration at a first depth. The semiconductor wafer is heated in a first thermal process to form radiation induced donors. Implantation energy and dose are chosen such that the semiconductor wafer has, after the first thermal process, an n-doped semiconductor region arranged between the second side and first depth, and the n-doped semiconductor region has, in the first vertical direction, a local maximum of a net doping concentration between the first depth and second side and a local minimum of the net doping concentration between the first depth and first maximum.Type: GrantFiled: June 24, 2014Date of Patent: September 5, 2017Assignee: Infineon Technologies AGInventors: Johannes Laven, Hans-Joachim Schulze, Stephan Voss, Alexander Breymesser, Alexander Susiti, Shuhai Liu, Helmut Oefner
-
Patent number: 9748102Abstract: A method for processing a semiconductor carrier is provided, the method including: providing a semiconductor carrier including a doped substrate region and a device region disposed over a first side of the doped substrate region, the device region including at least part of one or more electrical devices; and implanting ions into the doped substrate region to form a gettering region in the doped substrate region of the semiconductor carrier.Type: GrantFiled: October 11, 2016Date of Patent: August 29, 2017Assignee: INFINEON TECHNOLOGIES AGInventors: Johannes Laven, Hans-Joachim Schulze
-
Publication number: 20170110574Abstract: A semiconductor device includes transistor cells and control structures. The transistor cells include source zones of a first conductivity type and body zones of a second conductivity type. The source and body zones are formed in a semiconductor mesa formed from a portion of a semiconductor body. The control structures include first portions extending from a first surface into the semiconductor body on at least two opposing sides of the semiconductor mesa, second portions between the first portions and separated from the first surface by portions of the semiconductor mesa, and third portions connecting the first and the second portions and separated from the first surface by portions of the semiconductor mesa. Constricted sections of the semiconductor mesa separate third portions neighboring each other along a horizontal longitudinal extension of the semiconductor mesa.Type: ApplicationFiled: December 29, 2016Publication date: April 20, 2017Inventors: Johannes Laven, Hans-Joachim Schulze, Matteo Dainese, Peter Lechner, Roman Baburske
-
Patent number: 9613805Abstract: A method for forming a semiconductor device comprises forming an amorphous or polycrystalline semiconductor layer adjacently to at least one semiconductor doping region having a first conductivity type located in a semiconductor substrate. The method further comprises incorporating dopants into the amorphous or polycrystalline semiconductor layer during or after forming the amorphous or polycrystalline semiconductor layer. The method further comprises annealing the amorphous or polycrystalline semiconductor layer to transform at least a part of the amorphous or polycrystalline semiconductor layer into a substantially monocrystalline semiconductor layer and to form at least one doping region having the second conductivity type in the monocrystalline semiconductor layer, such that a p-n junction is formed between the at least one semiconductor doping region having the first conductivity type and the at least one doping region having the second conductivity type.Type: GrantFiled: December 11, 2015Date of Patent: April 4, 2017Assignee: Infineon Technologies AGInventors: Werner Schustereder, Holger Schulze, Johannes Laven, Roman Baburske, Rudolf Berger, Thomas Gutt
-
Publication number: 20170032966Abstract: A method for processing a semiconductor carrier is provided, the method including: providing a semiconductor carrier including a doped substrate region and a device region disposed over a first side of the doped substrate region, the device region including at least part of one or more electrical devices; and implanting ions into the doped substrate region to form a gettering region in the doped substrate region of the semiconductor carrier.Type: ApplicationFiled: October 11, 2016Publication date: February 2, 2017Inventors: Johannes LAVEN, Hans-Joachim SCHULZE
-
Patent number: 9536740Abstract: A description is given of a method for doping a semiconductor body, and a semiconductor body produced by such a method. The method comprises irradiating the semiconductor body with protons and irradiating the semiconductor body with electrons. After the process of irradiating with protons and after the process of irradiating with electrons, the semiconductor body is subjected to heat treatment in order to attach the protons to vacancies by means of diffusion.Type: GrantFiled: May 4, 2015Date of Patent: January 3, 2017Assignee: Infineon Technologies AGInventors: Hans-Joachim Schulze, Johannes Laven, Franz Josef Niedernostheide, Frank Dieter Pfirsch
-
Patent number: 9496351Abstract: A method for processing a semiconductor carrier is provided, the method including: providing a semiconductor carrier including a doped substrate region and a device region disposed over a first side of the doped substrate region, the device region including at least part of one or more electrical devices; and implanting ions into the doped substrate region to form a gettering region in the doped substrate region of the semiconductor carrier.Type: GrantFiled: January 5, 2016Date of Patent: November 15, 2016Assignee: INFINEON TECHNOLOGIES AGInventors: Johannes Laven, Hans-Joachim Schulze
-
Publication number: 20160322386Abstract: A semiconductor device includes a semiconductor substrate with a first surface. The device further includes one or more semiconductor devices formed or the first surface in an active area. The device further includes a plurality of cavities in the semiconductor substrate beneath the first surface. The device further includes dielectric support structures between each of the cavities and spaced apart from the first surface. The dielectric support structures support a part of the semiconductor substrate between the active area and the cavities. The dielectric support structures include an oxide.Type: ApplicationFiled: July 13, 2016Publication date: November 3, 2016Inventors: Johannes Laven, Matteo Dainese, Hans-Joachim Schulze
-
Publication number: 20160118466Abstract: A method for processing a semiconductor carrier is provided, the method including: providing a semiconductor carrier including a doped substrate region and a device region disposed over a first side of the doped substrate region, the device region including at least part of one or more electrical devices; and implanting ions into the doped substrate region to form a gettering region in the doped substrate region of the semiconductor carrier.Type: ApplicationFiled: January 5, 2016Publication date: April 28, 2016Inventors: Johannes Laven, Hans-Joachim Schulze
-
Patent number: 9263271Abstract: A method for processing a semiconductor carrier is provided, the method including: providing a semiconductor carrier including a doped substrate region and a device region disposed over a first side of the doped substrate region, the device region including at least part of one or more electrical devices; and implanting ions into the doped substrate region to form a gettering region in the doped substrate region of the semiconductor carrier.Type: GrantFiled: October 25, 2012Date of Patent: February 16, 2016Assignee: INFINEON TECHNOLOGIES AGInventors: Johannes Laven, Hans-Joachim Schulze
-
Publication number: 20150371858Abstract: A Magnetic Czochralski semiconductor wafer having opposing first and second sides arranged distant from one another in a first vertical direction is treated by implanting first particles into the semiconductor wafer via the second side to form crystal defects in the semiconductor wafer. The crystal defects have a maximum defect concentration at a first depth. The semiconductor wafer is heated in a first thermal process to form radiation induced donors. Implantation energy and dose are chosen such that the semiconductor wafer has, after the first thermal process, an n-doped semiconductor region arranged between the second side and first depth, and the n-doped semiconductor region has, in the first vertical direction, a local maximum of a net doping concentration between the first depth and second side and a local minimum of the net doping concentration between the first depth and first maximum.Type: ApplicationFiled: June 24, 2014Publication date: December 24, 2015Inventors: Johannes Laven, Hans-Joachim Schulze, Stephan Voss, Alexander Breymesser, Alexander Susiti, Shuhai Liu, Helmut Oefner
-
Publication number: 20150325440Abstract: A method for forming a semiconductor device includes depositing an epitaxial layer on a semiconductor substrate, forming an oxygen diffusion region within the epitaxial layer by oxygen diffusion from the semiconductor substrate into a part of the epitaxial layer and tempering at least the oxygen diffusion region of the epitaxial layer at a temperature between 400° C. and 480° C. for more than 15 minutes.Type: ApplicationFiled: May 7, 2015Publication date: November 12, 2015Inventors: Hans-Joachim Schulze, Johannes Laven