Abstract: A method is provided for installing a security-relevant portion of an application made available by an application provider in a security element of a terminal. The terminal requests the application from the application provider and receives the application. Subsequently, the received security-relevant portion of the application is transmitted to a trustworthy instance administrating the security element. The trustworthy instance subsequently installs the security-relevant portion of the application in the security element.

Abstract: A method is provided for installing a security-relevant portion of an application made available by an application provider in a security element of a terminal. The terminal requests the application from the application provider and receives the application. Subsequently, the received security-relevant portion of the application is transmitted to a trustworthy instance administrating the security element. The trustworthy instance subsequently installs the security-relevant portion of the application in the security element.

Abstract: A semiconductor memory device comprises a plurality of memory cells, each memory cell having a respective transistor. The transistor comprises a transistor body of a first conductivity type, a drain area and a source area each having a second conductivity type, wherein said drain area and source area are embedded in the transistor body on a first surface of said transistor body, a gate structure having a gate dielectric layer and a gate electrode. Said gate structure is arranged between said drain area and said source area. An emitter area of said first conductivity type is provided wherein said emitter area is arranged on top of said drain area.

Abstract: An apparatus for providing a signal for transmission via a signal line includes a controller circuit having an output for a signal indicating whether the signal line is or will be in an inactive state and a switching circuit coupled to the controller circuit and having an output coupled to the signal line. The output is switched between different signal levels, if the signal indicates that the signal line is in an inactive state.

Abstract: An integrated circuit including a gate electrode is disclosed. One embodiment provides a transistor including a first source/drain electrode and a second source/drain electrode. A channel is arranged between the first and the second source/drain electrode in a semiconductor substrate. A gate electrode is arranged adjacent the channel layer and is electrically insulated from the channel layer. A semiconductor substrate electrode is provided on a rear side. The gate electrode encloses the channel layer at least two opposite sides.

Abstract: A fin field effect transistor arrangement comprises a substrate and a first fin field effect transistor on and/or in the substrate. The first fin field effect transistor includes a fin in which a channel region is formed between a first source/drain region and a second source/drain region and above which a gate region is formed. A second fin field effect transistor is provided on and/or in the substrate including a fin in which a channel region is formed between a first source/drain region and a second source/drain region and above which a gate region is formed. The second fin field effect transistor is arranged laterally alongside the first fin field effect transistor, wherein a height of the fin of the first fin field effect transistor is greater than a height of the fin of the second fin field effect transistor.

Abstract: An apparatus being connectable as a latch stage into a asynchronous latch chain comprises a reception interface, wherein upon receipt of the first signal at the reception interface, the apparatus switches to one of the first power saving mode and a second power saving mode, depending on the second signal at the reception interface and wherein the apparatus offers a first power consumption and a first wake-up time in the first power saving mode, and a second power consumption and a second wake-up time in the second power saving mode.

Abstract: A semiconductor device having a stacked arrangement of a substrate and a first chip and a second chip is disclosed. In one embodiment, the first chip is arranged with a lower face on an upper face of the substrate; the second chip with a lower face on an upper face of the first chip, whereby a partial area of the upper face of the first chip that is adjacent to an edge of the first chip is uncovered by the second chip; a fifth wire contact pad is arranged on the uncovered area of the upper face of the first chip; a first bonding wire is arranged that is connected with a first wire contact pad of the substrate and the fifth wire contact pad of the first chip.

Abstract: Substrate having a first partial substrate with a carrier layer and a second partial substrate, which is bonded to the first partial substrate. The second partial substrate has an insulator layer, which is applied on the carrier layer and has at least two regions each having a different thickness, thereby forming a stepped surface of the insulator layer, and a semiconductor layer, which is applied to the stepped surface of the insulator layer and is formed at least partially epitaxially, wherein the semiconductor layer has a planar surface which is opposite to the stepped surface of the insulator layer. Transistors are formed on the semiconductor layer.

Abstract: In a method for producing a trench transistor, a substrate of a first conduction type is provided and a trench in the substrate and a gate dielectric in the trench are formed. A first conductive filling in the trench as a gate electrode on the gate dielectric and first source and drain regions are formed. An etched-back first conductive filling is produced by etching back the first conductive filling down to a depth below the first source and drain regions and second source and drain regions are formed. The second source and drain regions adjoin the first source and drain regions and extend to a depth at least as far as the etched-back first conductive filling. An insulation spacer above the etched-back first conductive filling is formed in the trench and a second conductive filling is provided in the trench as an upper part of the gate electrode.

Abstract: A semiconductor memory component comprises at least one memory cell. The memory cell comprises a semiconductor body comprised of a body region, a drain region and a source region, a gate dielectric, and a gate electrode. The body region comprises a first conductivity type and a depression between the source and drain regions, and the source and drain regions comprise a second conductivity type. The gate electrode is arranged at least partly in the depression and is insulated from the body, source, and drain regions by the gate dielectric. The body region further comprises a first continuous region with a first dopant concentration and a second continuous region with a second dopant concentration greater than the first dopant concentration. The first continuous region adjoins the drain region, the depression and the source region, and the second region is arranged below the first region and adjoins the first region.

Abstract: An integrated circuit arrangement and fabrication method is presented. The integrated circuit arrangement contains a semiconductor and a metal electrode. The contact area between a semiconductor and the electrode is increased without increasing the lateral dimensions using partial regions of the semiconductor and/or of the electrode that extend through a transition layer between the semiconductor and electrode.

Abstract: A method of manufacturing a transistor. In one embodiment, the method includes forming a gate electrode by defining a gate groove in the substrate. A plate-like portion is defined in each of the trenches at a position adjacent to the groove so that the two plate-like portions will be connected with the groove and the groove is disposed between two plate-like portions. In one embodiment, the two plate-like portions are defined by an etching process which selectively etches the isolating material of the isolation trenches with respect to the semiconductor substrate material. A gate insulating material is provided at an interface between the active area and the groove and the interface between the active area and the plate-like portions, and a gate electrode material is deposited so as to fill the groove and the two plate-like portions.

Abstract: A semiconductor device having a stacked arrangement of a substrate and a first chip and a second chip is disclosed. In one embodiment, the first chip is arranged with a lower face on an upper face of the substrate; the second chip with a lower face on an upper face of the first chip, whereby a partial area of the upper face of the first chip that is adjacent to an edge of the first chip is uncovered by the second chip; a fifth wire contact pad is arranged on the uncovered area of the upper face of the first chip; a first bonding wire is arranged that is connected with a first wire contact pad of the substrate and the fifth wire contact pad of the first chip.

Abstract: An apparatus interfaces a first circuit using a first supply voltage and a second circuit using a second supply voltage different from the first supply voltage. The apparatus includes a driver circuit having a driver network comprising driver supply voltage terminals connected to controllable switches. The controllable switches include resistive elements or are separated from resistive elements. A receiver circuit has a receiving network comprising a resistive element and receiver supply voltage terminals and a connection line connecting the driver circuit and the receiving circuit. The controllable switches have two switch configurations, a first switch configuration resulting in a high voltage on the connection line and a second switch configuration resulting in a low voltage on the connection line.

Abstract: An apparatus for providing a signal for transmission via a signal line includes a controller circuit having an output for a signal indicating whether the signal line is or will be in an inactive state and a switching circuit coupled to the controller circuit and having an output coupled to the signal line. The output is switched between different signal levels, if the signal indicates that the signal line is in an inactive state.

Abstract: An apparatus interfaces a first circuit using a first supply voltage and a second circuit using a second supply voltage different from the first supply voltage. The apparatus includes a driver circuit having a driver network comprising driver supply voltage terminals connected to controllable switches. The controllable switches include resistive elements or are separated from resistive elements. A receiver circuit has a receiving network comprising a resistive element and receiver supply voltage terminals and a connection line connecting the driver circuit and the receiving circuit. The controllable switches have two switch configurations, a first switch configuration resulting in a high voltage on the connection line and a second switch configuration resulting in a low voltage on the connection line.

Abstract: A memory buffer comprises a first asynchronous latch chain interface connectable to at least one of a memory controller and a memory buffer, a second data interface connected to a memory device, and a circuit comprising a buffer and a processor, the circuit being coupled to the first and the second interfaces, so that data can be passed between the first interface and the buffer and between the second interface and the buffer and so that the processor is capable of processing at least one of the data from the first interface to the second interface and the data from the second interface according to a data processing functionality, wherein the data processing functionality of the processor is changeable by a programming signal received via an interface of a memory buffer.

Abstract: An apparatus being connectable as a latch stage into a asynchronous latch chain comprises a reception interface, wherein upon receipt of the first signal at the reception interface, the apparatus switches to one of the first power saving mode and a second power saving mode, depending on the second signal at the reception interface and wherein the apparatus offers a first power consumption and a first wake-up time in the first power saving mode, and a second power consumption and a second wake-up time in the second power saving mode.

Abstract: An apparatus for transmitting signals over a signal line includes a transmitter with an output connectable to the signal line, for a synchronization signal in a power saving mode and a wanted signal in a normal mode of operation, wherein the synchronization signal has a reduced amplitude as compared to an amplitude of the wanted signal and has a periodic data pattern so that the synchronization signal permits maintaining an alignment of the synchronization signal and a reference signal in the receiver.