Abstract: According to various aspects, a memory cell is provided, the memory cell including: a capacitive memory structure; and a field-effect transistor structure including a gate isolation, wherein the capacitive memory structure and the field-effect transistor structure are coupled with one another to form a capacitive voltage divider, wherein the gate isolation includes at least one gate isolation layer, the at least one gate isolation layer including a material having a dielectric constant greater than 4, and wherein a thickness of the at least one gate isolation layer is in the range from 3 nm to 10 nm.

Abstract: According to various aspects, a memory cell is provided, the memory cell including: a capacitive memory structure including a first electrode; a field-effect transistor structure including a gate electrode; one or more insulator layers, one or more source/drain contact structures embedded in the one or more insulator layers to electrically contact the field-effect transistor structure, and a connection structure embedded in at least one of the one or more insulator layers, wherein the connection structure electrically conductively connects the first electrode of the capacitive memory structure and the gate electrode of the field-effect transistor structure with one another and is electrically floating, and one or more additional electrically insulating structures configured to prevent a leakage current-induced charging of the first electrode, the gate electrode, and the connection structure.

Abstract: A memory cell arrangement is provided that may include: a plurality of first control lines; a plurality of second control lines; a plurality of third control lines; each of a plurality of memory cell sets includes memory cells and is assigned to a corresponding one of the plurality of first control lines and includes at least a first memory cell subset addressable via the corresponding first control line, a corresponding one of the plurality of second control lines, and the plurality of third control lines, and at least a second memory cell subset addressable via the corresponding first control line, the plurality of second control lines, and a corresponding one of the plurality of third control lines. The corresponding one of the plurality of third control lines addresses the second memory cell subset of each memory cell set of the plurality of memory cell sets.

Abstract: According to various aspects, a memory cell is provided, the memory cell may include a field-effect transistor; a first control node and a second control node, a first capacitor structure including a first electrode connected to the first control node, a second electrode connected to a gate region of the field-effect transistor, and a remanent-polarizable region disposed between the first electrode and the second electrode of the first capacitor structure; and a second capacitor structure including a first electrode connected to the second control node, a second electrode connected to the gate region of the field-effect transistor. In some aspects, the first capacitor structure may have a first capacitance and the second capacitor structure may have a second capacitance different from the first capacitance.

Abstract: A memory cell arrangement is provided that may include: a plurality of electrode layers, wherein each of the plurality of electrode layers comprises a plurality of through holes, each of the plurality of through holes extending from a first surface to a second surface of a respective electrode layer; a plurality of electrode pillars, wherein each of the plurality of electrode pillars comprises a plurality of electrode portions, wherein each of the plurality of electrode portions is disposed within a corresponding one of the plurality of through holes; wherein the respective electrode layer and a respective electrode portion of the plurality of electrode portions form a first electrode and a second electrode of a capacitor and wherein at least one memory material portion is disposed in each of the plurality of through holes in a gap between the respective electrode layer and the respective electrode portion.

Abstract: According to various aspects, a memory cell arrangement is provided, the memory cell arrangement including a control circuit configured to carry out a de-trapping writing scheme to write at least one memory cell of the memory cell arrangement into a memory state, the de-trapping writing scheme including providing one or more write voltage pulses and one or more de-trapping voltage pulses at the at least one memory cell, wherein the one or more de-trapping voltage pulses have opposite polarity with respect to the one or more write voltage pulses, and wherein one or more properties of the one or more write voltage pulses and of the one or more de-trapping voltage pulses are varied as long as the memory cell is not in the memory state.

Abstract: A memory cell arrangement is provided that may include: a plurality of electrode layers, wherein each of the plurality of electrode layers comprises a plurality of through holes, each of the plurality of through holes extending from a first surface to a second surface of the respective electrode layer; a plurality of electrode pillars, wherein each of the plurality of electrode pillars comprises a plurality of electrode portions, wherein each of the plurality of electrode portions is disposed within a corresponding one of the plurality of through holes; wherein at least one remanent-polarizable portion is disposed in each of the plurality of through holes in a gap between the respective electrode layer and the respective electrode portion.

Abstract: According to various aspects, a memory cell is provided, the memory cell may include a field-effect transistor; a first control node and a second control node, a first capacitor structure including a first electrode connected to the first control node, a second electrode connected to a gate region of the field-effect transistor, and a remanent-polarizable region disposed between the first electrode and the second electrode of the first capacitor structure; and a second capacitor structure including a first electrode connected to the second control node, a second electrode connected to the gate region of the field-effect transistor. In some aspects, the first capacitor structure may have a first capacitance and the second capacitor structure may have a second capacitance different from the first capacitance.

Abstract: A memory cell arrangement is provided that may include: a plurality of first control lines; a plurality of second control lines; a plurality of third control lines; each of a plurality of memory cell sets includes memory cells and is assigned to a corresponding one of the plurality of first control lines and includes at least a first memory cell subset addressable via the corresponding first control line, a corresponding one of the plurality of second control lines, and the plurality of third control lines, and at least a second memory cell subset addressable via the corresponding first control line, the plurality of second control lines, and a corresponding one of the plurality of third control lines. The corresponding one of the plurality of third control lines addresses the second memory cell subset of each memory cell set of the plurality of memory cell sets.

Abstract: A memory cell arrangement is provided that may include: a plurality of electrode layers, wherein each of the plurality of electrode layers comprises a plurality of through holes, each of the plurality of through holes extending from a first surface to a second surface of the respective electrode layer; a plurality of electrode pillars, wherein each of the plurality of electrode pillars comprises a plurality of electrode portions, wherein each of the plurality of electrode portions is disposed within a corresponding one of the plurality of through holes; wherein at least one remanent-polarizable portion is disposed in each of the plurality of through holes in a gap between the respective electrode layer and the respective electrode portion.

Abstract: According to various embodiments, a memory cell may include: a field-effect transistor structure comprising a channel region and a gate structure disposed at the channel region, the gate structure comprising a gate electrode structure and a gate isolation structure disposed between the gate electrode structure and the channel region; and a memory structure comprising a first electrode structure, a second electrode structure, and at least one remanent-polarizable layer disposed between the first electrode structure and the second electrode structure; wherein the first electrode structure of the memory structure is electrically conductively connected to the gate electrode structure of the field-effect transistor structure.

Abstract: According to various embodiments, a memory cell may include: a field-effect transistor structure comprising a channel region and a gate structure disposed at the channel region, the gate structure comprising a gate electrode structure and a gate isolation structure disposed between the gate electrode structure and the channel region; and a memory structure comprising a first electrode structure, a second electrode structure, and at least one remanent-polarizable layer disposed between the first electrode structure and the second electrode structure; wherein the first electrode structure of the memory structure is electrically conductively connected to the gate electrode structure of the field-effect transistor structure.

Abstract: According to various embodiments, a memory cell may include: a field-effect transistor structure comprising a channel region and a gate structure disposed at the channel region, the gate structure comprising a gate electrode structure and a gate isolation structure disposed between the gate electrode structure and the channel region; and a memory structure comprising a first electrode structure, a second electrode structure, and at least one remanent-polarizable layer disposed between the first electrode structure and the second electrode structure; wherein the first electrode structure of the memory structure is electrically conductively connected to the gate electrode structure of the field-effect transistor structure.

Abstract: According to various embodiments, a memory cell may include: a field-effect transistor structure comprising a channel region and a gate structure disposed at the channel region, the gate structure comprising a gate electrode structure and a gate isolation structure disposed between the gate electrode structure and the channel region; and a memory structure comprising a first electrode structure, a second electrode structure, and at least one remanent-polarizable layer disposed between the first electrode structure and the second electrode structure; wherein the first electrode structure of the memory structure is electrically conductively connected to the gate electrode structure of the field-effect transistor structure.

Abstract: Apparatus for bidirectional transmission of optical signals between two stations connected by a light transmission path of optical fibers, each station including a laser module comprised of a laser diode and an adjacent monitor diode, the latter performing the dual functions of detecting light emitted by such laser diode in its transmission mode, and for detecting light transmitted from the other station when such adjacent laser diode is not in its transmission mode.