Abstract: Optical disk systems comprising photo detectors (1) for detecting optical disks comprising amplifiers and slicers (2-5) and delay-difference detectors (6) for detecting delay differences in sliced amplified detection signals are improved by installing delaylineless delay-difference detectors (6) comprising combinatorial-logic circuits (7,8) like inverters, ORs, NORs, ANDs, NANDs and sequential-logic circuits (11-18) like SetResetFlipFlops. Without the prior art delay lines, said delay-difference detectors (6) are of a lower complexity and low costly and can be well integrated. By introducing a first pair of sequential-logic circuits (11,12,15,16) for detecting delay differences between rising edges and a second pair of sequential-logic circuits (13,14,17,18) for detecting delay differences between falling edges, both kinds of edges are being used and the influence of time-jitter is less compared to the situation where just one kind of edge is used.

Abstract: An optical disk system includes at least one photo detector connected with a variable gain amplifier, a slicer, and a generator which is in the feedback path between the slicer and amplifier. A differential time delay detector provides the output of the optical disk system. The generator is configured for controlling the amplifier non-linearly so that time constants of the control loop of the amplifier which depend upon the level of the input signals are compensated and the timing behavior of the control loop of the amplifier has a more continuous character. A capacitor forms part of an integrator for making the mean value of the output voltage signal of the slicer equal to zero.

Abstract: The invention relates to a method of reading of magnetic information. In an example embodiment, a read head includes a magneto-resistive rod polarized with an electrical signal. The magneto-resistive rod supplies a data signal whose variations are representative of magnetic-field variations to which the read head is exposed. Included in the embodiment, there is a compression of the data signal triggered when a thermal asperity is detected.

Abstract: A receiver for restoring a data signal from a data input signal, comprises a data detector and a control signal generator coupled to the data detector for controlling one or more loops in the data detector, such as an automatic gain control, an equalizer adaptation and/or a timing recovery loop. The receiver also comprises erasure means for generating an instantaneous erasure information signal in case the data input signal to be restored falls within an erasure zone, which erasure means are coupled to the control signal generator for essentially instantaneous use of the instantaneous erasure information for accurate loop control. Preferably the respective control signals are kept constant in time during periods of erasure.

Abstract: A current mirror circuit is described which includes a current input terminal (14A), a current output terminal (14B) and a common terminal (14C). A first controllable semiconductor element (T1) is arranged between the current input terminal (14A) and the common terminal (14C). A second controllable semiconductor element (T2) is arranged between the current output terminal (14B) and the common terminal (14C). The controllable semiconductor elements (T1, T2) have interconnected control electrodes (T1A, T2A) which are also coupled to a bias voltage source (VBIAS), for biasing said control electrodes at a reference voltage. The circuit further includes a transconductance stage (12) with an input (12A) coupled to the current input terminal (14A) and an output (12B) coupled to the common terminal (14C). The control electrodes (T1A, T2A) are coupled to the common terminal (14C) via a third controllable semiconductor element (T3).

Abstract: A new embedded-servo format is proposed for use in disk drives, preferably hard disk drives. It is based on biphase modulation (more generally, p-phase modulation, where p>1) and offers significant advantages, in terms of SNR and timing content, over existing formats. It is shown that for biphase, at the low linear densities typically employed for servo information, near maximum-likelihood performance may be attained by a simple bit-detector consisting of a full-response linear equalizer and a binary slicer. When compared with an optimal detector for the commonly used technique of dibit signalling, a SNR gain of some 4 dB is achieved. The same equalizer may be used as the basis for near-maximum-likelihood Position Error Signal (PES) amplitude estimation and timing recovery. Investigations carried out on a practical servo demodulator based on a 5th order analog filter show that, at typical linear densities, this ideal performance is closely approached.

Abstract: A current mirror circuit is described which includes a current input terminal (14A), a current output terminal (14B) and a common terminal (14C). A first controllable semiconductor element (T1) is arranged between the current input terminal (14A) and the common terminal (14C). A second controllable semiconductor element (T2) is arranged between the current output terminal (14B) and the common terminal (14C). The controllable semiconductor elements (T1, T2) havie interconnected control electrodes (T1A, T2A) which are also coupled to a bias voltage source (VBIAS), for biasing said control electrodes at a reference voltage. The circuit further includes a transconductance stage (12) with an input (12A) coupled to the current input terminal (14A) and an output (12B) coupled to the common terminal (14C). The control electrodes (T1A, T2A) are coupled to the common terminal (14C) via a third controllable semiconductor element (T3).

Abstract: The invention relates to a method of reading magnetic information by means of a read head including a magneto-resistive rod RMR, which is to be polarized by means of an electrical signal Imr and serves to supply a data signal Vmr whose variations are representative of the magnetic-field variations to which the read head is exposed.

Abstract: A receiver for restoring a data signal from a data input signal, comprises a data detector and a control signal generator coupled to the data detector for controlling one or more loops in the data detector, such as an automatic gain control, an equalizer adaptation and/or a timing recovery loop. The receiver also comprises erasure means for generating an instantaneous erasure information signal in case the data input signal to be restored falls within an erasure zone, which erasure means are coupled to the control signal generator for essentially instantaneous use of the instantaneous erasure information for accurate loop control. Preferably the respective control signals are kept constant in time during periods of erasure.

Abstract: A circuit arrangement for effectively correcting the absolute values of a plurality of impedances when they already have impedance values in the correct ratio to each other. Current going through each impedance is multiplied by a ratio derived from a precision impedance. The circuit is particularly useful in integrated circuit technology where impedance ratios can be accurately controlled but not so readily the absolute values of the impedances.

Abstract: A current stabilizing arrangement which includes a three-terminal circuit with an input terminal and an output terminal, at which output terminal a current with a negative temperature coefficient appears, while a constant current is applied to the input terminal. The arrangement further comprises a current source circuit, which supplies a current with a positive temperature coefficient and a squaring circuit to which a current is applied which is proportional to the current of the current source circuit, and whose output current, added to the output currents of the current-source circuit and of the three-terminal circuit, results in a temperature independent current. The temperature independent current thus obtained is applied to the input of a current mirror circuit, whose output current is fed to the input terminal of the three-terminal circuit.

Abstract: An anti-reciprocal network including at least a first and a second port each with two terminals, the ports being included in a closed loop which has at least three impedance elements. The network also includes two amplifiers which are coupled to the two ports, wherein each of the amplifiers includes a transistor.