Abstract: High-speed RF differential, Quadrature, divide-by-2 clock divider designs are based on inverters and clocking circuits connected in a serial ring formation. In one embodiment, only NMOS transistors are used in the inverters, and only PMOS transistors are used in the clocking circuits. This structure uses only 12 transistors, The input can be coupled directly to a VCO output, and provides minimum loading, as each VCO output is connected to only two transistors. Another embodiment comprises clocked inverter stages connected in a serial ring configuration with inverters between stages. The RF clock (or VCO signal) is used at the outer side of the inverters for speed improvement. In both circuits, positive and negative clock inputs are connected alternately at each stage of the ring.

Abstract: A digital phase locked loop (DPLL) operates in the frequency domain. The period (and hence frequency) of a reference frequency clock signal is determined by sampling with a (higher frequency) digitally controlled oscillator (DCO) clock. The period is compared to the period representation of a desired frequency, and the frequency error signal is integrated in a loop filter and applied as a control input to the DCO. To prevent spurious emissions resulting from the accumulation of quantization errors in the frequency determination and comparison operations, the arrival time of state transition edges of the reference frequency clock signal are randomized prior to sampling. The edge randomization control signal preferably has a triangular probability density function, and its spectrum has most significant energy outside the loop bandwidth of the DPLL; hence, the spurious emissions caused by the accumulation of quantization errors are filtered out by the loop filter.

Abstract: A sampler circuit comprises a plurality of series-connected sampler cells and a detector circuit. Each successive stage comprises twice the number of sampler cells, in parallel, as the previous stage, and is clocked at half the sampling frequency of the previous stage. Each sampler cell comprises two parallel branches of series-connected clocked inverters. A clocked inverter is operative to invert an applied signal during one phase of an applied sampling clock, and to render a high impedance output during the other sampling clock phase. Successive clocked inverters are clocked with opposite (i.e., positive/negative) versions of the sampling clock. The detector circuit examines the outputs of the last stage of sampler cells, and may for example comprise an OR function to detect a state transition in an applied input signal. The sampler circuit exhibits immunity to metastability and low power consumption.

Abstract: An RF power amplifier for a polar transmitter converts an amplitude component signal into a 1-bit digital amplitude signal, which is fed to a digital finite impulse response filter. Successive taps of the filter each have an RF amplification stage arranged to amplify successively delayed versions of the 1-bit digital amplitude signal, the amplifying being according to a respective tap coefficient, and according to the RF carrier modulated by the phase component. The filter is arranged to combine the outputs of the taps to provide the amplified RF signal. The power amplifier uses a one bit stream which therefore has only two states (2 values), thus achieving linearity in principle. Device mismatch between taps does not lead to non-linearity or distortion.

Abstract: An electronic circuit comprises a delay circuit that with a chain of saw tooth delay stages (10a-d), coupled in a loop to form an oscillator for example. Each stage comprises an integrating circuit (104) and a current modulator (106) coupled to the integrating circuit (104). Each stage triggers a transition in the next stage when the integration result reaches a level defined by a reference voltage. Correlating circuitry (102, 30, 32, 34) is provided with current outputs to generate currents to the current modulators (106) and reference voltages for the saw tooth delay stages (10a-d). The reference voltages are generated at least partly from a common reference (102c), so that noise in the currents from the current modulators (106) and reference voltages is correlated in a way that at least partly cancels the effect of the noise on the delay time.

Abstract: An electronic circuit comprises a delay circuit that with a chain of saw tooth delay stages (10a-d), coupled in a loop to form an oscillator for example. Each stage comprises an integrating circuit (104) and a current modulator (106) coupled to the integrating circuit (104). Each stage triggers a transition in the next stage when the integration result reaches a level defined by a reference voltage. Correlating circuitry (102, 30, 32, 34) is provided with current outputs to generate currents to the current modulators (106) and reference voltages for the saw tooth delay stages (10a-d). The reference voltages are generated at least partly from a common reference (102c), so that noise in the currents from the current modulators (106) and reference voltages is correlated in a way that at least partly cancels the effect of the noise on the delay time.

Abstract: A ring oscillator according to the invention comprises a closed chain of at least two modules (1, 2). At least one of the modules (1, 2) comprises a primary (10) and a second amplifier stage (11) and combination means (12) for combining output signals of the primary (10) the secondary amplifier stage (11) so as to generate an output signal of the module. The amplifier stages (10, 11) have a mutually different delay and the primary (10) and the secondary am amplifier stage (11) are each coupled to an input (13) of the module (1). The ring oscillator further comprises a control unit (4) for generating a first (C1) and a second auxiliary control signal (C2) for controlling the amplification of the primary amplifier stage (10) and the secondary amplifier stage (11) in response to an input control signal (Co) representative for a desired frequency for the ring oscillator.

Abstract: A minimum detector arrangement comprising a minimum detector for detecting a minimum value of an input signal and generating a first output signal indicative for an approximation of the minimum value of the input signal. The minimum detector arrangement is characterized in that it further comprises a replica of the minimum detector for receiving another input signal and generating a second output signal indicative for an error in said approximation. The minimum detector and the replica of the minimum detector being coupled to a signal combination unit for generating a third output signal indicative for a more accurate approximation of the minimum value of the input signal.

Abstract: A ring oscillator according to the invention comprises a closed chain of at least two modules (1, 2). At least one of the modules (1, 2) comprises a primary (10) and a secondary amplifier stage (11) and combination means (12) for combining output signals of the primary (10) and the secondary amplifier stage (11) so as to generate an output signal of the module. The amplifier stages (10, 11) have a mutually different delay and the primary (10) and the secondary amplifier stage (11) are each coupled to an input (13) of the module (1). The ring oscillator further comprises a control unit (4) for generating a first (C1) and a second auxiliary control signal (C2) for controlling the amplification of the primary amplifier stage (10) and the secondary amplifier stage (11) in response to an input control signal (Co) representative for a desired frequency for the ring oscillator.