Abstract: A charging pad capable of charging a receiver according to a predetermined procedure is disclosed. The charging pad may have a plurality of charging coils and a controller for selecting an appropriate coil for charging the receiver. The receiver communicates with the charging pad via NFC, thereby indicating to the charging pad the appropriate procedure for charging the receiver. The controller then selects the appropriate coil and directs charging according to the appropriate procedure.

Abstract: A battery cell measurement system comprising a signal generator coupled to a pulse density modulation circuit generating a control signal which drives a switch connected between a first terminal of a battery cell and a first terminal of a bleeding impedance, a second terminal of the bleeding impedance being coupled to a second battery cell terminal. The first terminal is coupled to a first terminal of a second switch. The second terminal is coupled to a first terminal of a third switch. A second terminal of the second switch and second terminal of the third switch are coupled and are further coupled to a low-pass filter. A signal generated by the low-pass filter is inputted into an analog to digital converter, which provides a signal representative of either a signal across the bleeding impedance, or a signal between the battery cell terminals.

Abstract: Various aspects of the present disclosure are directed to monitoring battery cells. In accordance with various embodiments, an energy storage cell apparatus includes a current injection circuit that separately inject current into individual ones of a plurality of battery cells that store energy, and an impedance-detection circuit detects an impedance characteristic of each of the plurality of battery cells in response to the injected current. A filter circuit receives impedance data regarding the detected impedance characteristic and separates low-frequency components of the impedance data from high-frequency components of the impedance data. A memory circuit stores data corresponding to high-bandwidth data including both the low-frequency components and the high-frequency components, and an access circuit provides the low-frequency components for the plurality of battery cells to a battery pack controller.

Abstract: Various embodiments relate to an in-cell battery management device including: an integrated circuit (IC) including a controller, a resistive balancer, a voltage sensor, and a pressure sensor; and an IC package that encloses the IC having a hole over the pressure sensor wherein the hole allows the pressure sensor to measure pressure in a battery cell; wherein the IC package is contact with the battery cell.

Abstract: Various aspects of the present disclosure are directed to monitoring battery cells. In accordance with various embodiments, an energy storage cell apparatus includes a current injection circuit that separately inject current into individual ones of a plurality of battery cells that store energy, and an impedance-detection circuit detects an impedance characteristic of each of the plurality of battery cells in response to the injected current. A filter circuit receives impedance data regarding the detected impedance characteristic and separates low-frequency components of the impedance data from high-frequency components of the impedance data. A memory circuit stores data corresponding to high-bandwidth data including both the low-frequency components and the high-frequency components, and an access circuit provides the low-frequency components for the plurality of battery cells to a battery pack controller.

Abstract: Various aspects of the present disclosure are directed to monitoring battery cells. In accordance with various embodiments, a battery pack having a plurality of battery cells connected in series is monitored. Current is separately injected into individual ones of the plurality of battery cells, such as by operating a balancing circuit coupled across an individual cell, to inject current (e.g., positive or negative) into the cell. For each of the battery cells, an output is provided to indicate cell voltage of the battery cell responsive to the current injected therein. An output indicative of current through each of the battery cells is provided as well. From the respective outputs as corresponding to each individual cell, amplitude and phase characteristics of the current and voltage outputs for each of the cells are extracted to provide an indication of an impedance characteristic of the cell(s).

Abstract: A battery cell measurement system comprising a signal generator coupled to a pulse density modulation circuit generating a control signal which drives a switch connected between a first terminal of a battery cell and a first terminal of a bleeding impedance, a second terminal of the bleeding impedance being coupled to a second battery cell terminal. The first terminal is coupled to a first terminal of a second switch. The second terminal is coupled to a first terminal of a third switch. A second terminal of the second switch and second terminal of the third switch are coupled and are further coupled to a low-pass filter. A signal generated by the low-pass filter is inputted into an analog to digital converter, which provides a signal representative of either a signal across the bleeding impedance, or a signal between the battery cell terminals.

Abstract: An energy storage cell arrangement has a shared inductor (60). A switching arrangement (62) is controllable such that it is able to couple one side of the inductor to any one of a first set of cell terminals, and to couple the other side of the inductor to any one of a second set of cell terminals, wherein the first and second sets of cell terminals together comprise all cell terminals of the series arrangement. In this way, energy can be transferred between cells in a configurable way, using a shared inductor.

Abstract: There is disclosed a charge balancing circuit (CBC) and method (10, 20) for balancing charge storage elements (CSE1—1, CSE1—2, CSE2—2) of a charge storage device (CSD). The charge storage device comprises at least two series connected chains (CHN1, CHN2) of charge storage elements. The charge balancing circuit (CBC) connects a first charge storage element (CSE1—1) of a first chain (CHN1) in parallel with a first charge storage element (CSE1—2) of a second chain (CHN2) during a first period of time (?1), and connects the first charge storage element (CSE1—1) of the first chain (CHN1) in parallel with a second charge storage element (CSE2—2) of the second chain (CHN2) during a second period of time (?2).

Abstract: The present invention relates to a phase locked loop arrangement having an oscillator circuit (240) controlled in response to an output signal of a phase or frequency detection circuit (210), wherein change control (130) are provided for generating a blocking signal in response to the outputs of a first timer (110) to which a predetermined threshold frequency is supplied and a second timer (112) to which an output frequency of the oscillator circuit (240) is supplied. Based on the blocking signal, blocking (260) suppress supply of the output signal to said oscillator circuit (240). Thereby, the output frequency of the PLL arrangement can be prevented from changing beyond the frequency threshold, while only one PLL circuit is required.

Abstract: The present invention relates to a phase locked loop arrangement having an oscillator circuit (240) controlled in response to an output signal of a phase or frequency detection circuit (210), wherein change control means (130) are provided for generating a blocking signal in response to the outputs of a first timer means (110) to which a predetermined threshold frequency is supplied and a second timer means (112) to which an output frequency of the oscillator circuit (240) is supplied. Based on the blocking signal, blocking means (260) suppress supply of the output signal to said oscillator circuit (240). Thereby, the output frequency of the PLL arrangement can be prevented from changing beyond the frequency threshold, while only one PLL circuit is required.

Abstract: A circuit module contains a sub-circuit that is capable of providing a level of performance dependent on the version number that is stored in a version number memory. The version number is passed to the sub-circuit from a write-protected memory to the version memory in the multiplex mode with normal operating signals for the sub-circuit. In one embodiment various commands for the circuit module are received from outside the circuit module and distributed in the circuit module via a communication bus. A watchdog monitors received commands for an update command that commands updating of the version number in the version number memory and if so it passes said update command to the communication bus, replacing a version number in the update command by a version number from the write-protected memory. In another embodiment the version number is passed to the sub-circuit in time-slot multiplexing with the signals that are processed, for example in a blanking period of a video signal that is being processed.

Abstract: The invention relates to a device that comprises a memory circuit with memory cells that use floating gate storage transistors, which are conventionally called non-volatile memory cells. A particular embodiment relates to a teletext circuit. A teletext processing circuit comprising a decoder logic circuit and a memory circuit integrated together in an integrated circuit, the memory circuit comprising memory cells for storing teletext page data, the memory cells comprising floating gate storage transistors to store the teletext page data. The page data from memory is used to control the content of displayed teletext images.

Abstract: A display apparatus comprises a signal converter (SC) which converts input text information (IT) and interlaced input video information (IV) with a number of video lines (Li) in a video field (Fi) into a display signal (DS) which comprises display text (Ti) and display video (Vi). An addressing circuit (AD) addresses a display screen (DSC) of the display apparatus in successive non-interlaced display fields (Fi) which have a duration substantially equal to the video field (Fi) and a number of display lines (DLi) which is substantially twice the number of video lines (Li). The signal converter (SC) has an output to supply the display signal (DS) in which the display video (Vi) is present on odd or even display lines (DLi) only, in respective successive display fields (Fi), and in which the display text (Ti) is present on same display lines (DLi) of the successive display fields (Fi).