Abstract: A receiver having a phase-locked loop (PLL) for synchronizing its oscillator with a carrier (CA). A calibration circuit (CAL) calibrates the phase-locked loop's oscillator (OSC) in the following manner. It measures (FMC) the frequency difference (dF) between a nominal frequency (Fnom) of the carrier (CA) and a frequency (Fosc) of the phase-locked loop's oscillator (OSC). Furthermore, it adjusts the frequency (Fosc) of the PLL oscillator in accordance with the measured frequency difference (dF). As a result, the phase-locked loop's oscillator will be substantially tuned to the nominal frequency of the carrier. The actual frequency of the carrier may differ from the nominal frequency. In general, such a difference will be sufficiently small for the phase-locked loop (PLL) to capture the carrier (CA).

Abstract: TV receiver including an RF section, a mixer stage to which a tuning frequency is applied from a tuning oscillator, an IF section, a synchronous detection device and a frequency and phase-locked loop circuit having a PLL and a FLL, the IF section being coupled to a phase detector of the PLL and to a frequency detection device of the FLL, the phase detector and frequency detection device being commonly coupled to a loop branch having the two loops in common and incorporating a loop filter and a controllable oscillator, the controllable oscillator applying a local in-phase carrier to the synchronous detection device and a local phase quadrature carrier to the phase detector.

Abstract: A third-order all-pass network for a delay circuit is formed by four coupled transconductors (G.sub.10 to G.sub.13) which are each represented by two transistors whose bases constitute the inputs and whose collectors constitute the outputs of the transconductor. A first input of these transconductors (G.sub.10 to G.sub.13) is connected to ground (3). Between the second inputs (25,26) of the first transconductor (G.sub.10) and the second transconductor (G.sub.11) a first capacitor (C.sub.1) is arranged, between the second inputs (26,27) of the second transconductor (G.sub.11) and the third transconductor (G.sub.12) a second capacitor (C2) is arranged, and between the second inputs (27,28) of the third transconductor (G.sub.12) and the fourth transconductor (G.sub.13) and a third capacitor (C3) is arranged. Further, a fourth capacitor (C4) is arranged between the second inputs (25,27) of the first transconductor (G.sub.10) and the third transconductor (G.sub.

Abstract: A third-order all-pass network for a delay circuit is formed by four coupled transconductors (G.sub.10 to G.sub.13) which are each represented by two transistors whose bases constitute the inputs and whose collectors constitute the outputs of the transconductor. A first input of these transconductors (G.sub.10 to G.sub.13) is connected to ground (3). Between the second inputs (25,26) of the first transconductor (G.sub.10) and the second transconductor (G.sub.11) a first capacitor (C.sub.1) is arranged, while between the second imputs (26,27) of the second transconductor (G.sub.11) and the third transconductor (G.sub.12) a second capacitor (C2) is arranged, and between the second inputs (27,28) of the third transconductor (G.sub.12) and the fourth transconductor (G.sub.13) a third capacitor (C3) is arranged. Further, a fourth capacitor (C4) is arranged between the second inputs (25,27) of the first transconductor (G.sub.10) and the third transconductor (G.sub.