Patents by Inventor Johannes Schoiswohl
Johannes Schoiswohl has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9472541Abstract: A method for manufacturing an electronic module is disclosed. In an embodiment the method includes providing a passive component having an upper surface of a first area, and electrically and mechanically attaching a first semiconductor chip having a lower surface of a second area that is smaller than the first area to the passive component, wherein the lower surface of the first semiconductor chip is arranged on the upper surface of the passive component, and wherein the first semiconductor chip comprises a vertical field-effect transistor.Type: GrantFiled: June 20, 2015Date of Patent: October 18, 2016Assignee: Infineon Technologies AGInventors: Martin Standing, Johannes Schoiswohl
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Publication number: 20150371979Abstract: A method for manufacturing an electronic module is disclosed. In an embodiment the method includes providing a passive component having an upper surface of a first area, and electrically and mechanically attaching a first semiconductor chip having a lower surface of a second area that is smaller than the first area to the passive component, wherein the lower surface of the first semiconductor chip is arranged on the upper surface of the passive component, and wherein the first semiconductor chip comprises a vertical field-effect transistor.Type: ApplicationFiled: June 20, 2015Publication date: December 24, 2015Inventors: Martin Standing, Johannes Schoiswohl
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Patent number: 9070642Abstract: An electronic module includes a first semiconductor chip and a passive component, wherein the first semiconductor chip is arranged on a surface of the passive component.Type: GrantFiled: September 14, 2011Date of Patent: June 30, 2015Assignee: Infineon Technologies AGInventors: Martin Standing, Johannes Schoiswohl
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Patent number: 8946767Abstract: A semiconductor device and method are disclosed. One embodiment provides a semiconductor die with a first n-type channel FET and a second n-type channel FET. A source of the first n-type channel FET and a drain of the second n-type channel FET are electrically coupled to at least one contact area at a first side. A drain of the first n-type channel FET, a gate of the first n-type channel FET, a source of the second n-type channel FET and the gate of the second n-type channel FET are electrically coupled to contact areas at a second side. Contact areas of the first n-type channel FET and the second n-type channel FET are electrically separated from each other.Type: GrantFiled: June 4, 2012Date of Patent: February 3, 2015Assignee: Infineon Technologies Austria AGInventors: Oliver Haeberlen, Walter Rieger, Martin Vielemeyer, Lutz Goergens, Martin Poelzl, Milko Paolucci, Johannes Schoiswohl, Sonja Krumrey
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Publication number: 20130140673Abstract: A semiconductor device and method are disclosed. One embodiment provides a semiconductor die with a first n-type channel FET and a second n-type channel FET. A source of the first n-type channel FET and a drain of the second n-type channel FET are electrically coupled to at least one contact area at a first side. A drain of the first n-type channel FET, a gate of the first n-type channel FET, a source of the second n-type channel FET and the gate of the second n-type channel FET are electrically coupled to contact areas at a second side. Contact areas of the first n-type channel FET and the second n-type channel FET are electrically separated from each other.Type: ApplicationFiled: June 4, 2012Publication date: June 6, 2013Applicant: INFINEON TECHNOLOGIES AUSTRIA AGInventors: Oliver Haeberlen, Walter Rieger, Martin Vielemeyer, Lutz Goergens, Martin Poelzl, Milko Paolucci, Johannes Schoiswohl, Joachim Krumrey
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Publication number: 20130062706Abstract: An electronic module includes a first semiconductor chip and a passive component, wherein the first semiconductor chip is arranged on a surface of the passive component.Type: ApplicationFiled: September 14, 2011Publication date: March 14, 2013Applicant: Infineon Technologies AGInventors: Martin Standing, Johannes Schoiswohl
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Patent number: 8193559Abstract: One aspect is monolithic semiconductor switches and method for manufacturing. One embodiment provides a semiconductor die with a first n-type channel FET and a second n-type channel FET. A source of the first n-type channel FET and a drain of the second n-type channel FET are electrically coupled to at least one contact area at a first side of the semiconductor die, respectively. A drain of the first n-type channel FET, a gate of the first n-type channel FET, a source of the second n-type channel FET and the gate of the second n-type channel FET are electrically coupled to contact areas at a second side of the semiconductor die opposite to the first side, respectively. The contact areas of the drain of the first n-type channel FET, of the gate of the first n-type channel FET, of the source of the second n-type channel FET and of the gate of the second n-type channel FET are electrically separated from each other, respectively.Type: GrantFiled: April 7, 2011Date of Patent: June 5, 2012Assignee: Infineon Technologies Austria AGInventors: Oliver Haeberlen, Walter Rieger, Martin Vielemeyer, Lutz Goergens, Martin Poelzl, Milko Paolucci, Johannes Schoiswohl, Joachim Krumrey, Sonja Krumrey, legal representative
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Publication number: 20110241170Abstract: One aspect is monolithic semiconductor switches and method for manufacturing. One embodiment provides a semiconductor die with a first n-type channel FET and a second n-type channel FET. A source of the first n-type channel FET and a drain of the second n-type channel FET are electrically coupled to at least one contact area at a first side of the semiconductor die, respectively. A drain of the first n-type channel FET, a gate of the first n-type channel FET, a source of the second n-type channel FET and the gate of the second n-type channel FET are electrically coupled to contact areas at a second side of the semiconductor die opposite to the first side, respectively. The contact areas of the drain of the first n-type channel FET, of the gate of the first n-type channel FET, of the source of the second n-type channel FET and of the gate of the second n-type channel FET are electrically separated from each other, respectively.Type: ApplicationFiled: April 7, 2011Publication date: October 6, 2011Applicant: INFINEON TECHNOLOGIES AUSTRIA AGInventors: Oliver Haeberlen, Walter Rieger, Martin Vielemeyer, Lutz Goergens, Martin Poelzl, Milko Paolucci, Johannes Schoiswohl, Joachim Krumrey, Sonja Krumrey
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Patent number: 7943955Abstract: One aspect is monolithic semiconductor switches and method for manufacturing. One embodiment provides one semiconductor die with a first and a second FET. One of source/drain of the first FET and one of source/drain of the second FET are electrically coupled to at least one contact area at a first side of one semiconductor die, respectively. The other one of source/drain of the first FET, a gate of the first FET, the other one of source/drain of the second FET and the gate of the second FET are electrically coupled to contact areas at a second side of the one semiconductor die opposite to the first side, respectively. The contact areas of the other one of source/drain of the first FET, of the gate of the first FET, of the other one of source/drain of the second FET and of the gate of the second FET are electrically separated from each other, respectively.Type: GrantFiled: January 27, 2009Date of Patent: May 17, 2011Assignee: Infineon Technologies Austria AGInventors: Oliver Haeberlen, Walter Rieger, Lutz Goergens, Martin Poelzl, Johannes Schoiswohl, Joachim Krumrey
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Publication number: 20100187605Abstract: One aspect is monolithic semiconductor switches and method for manufacturing. One embodiment provides one semiconductor die with a first and a second FET. One of source/drain of the first FET and one of source/drain of the second FET are electrically coupled to at least one contact area at a first side of one semiconductor die, respectively. The other one of source/drain of the first FET, a gate of the first FET, the other one of source/drain of the second FET and the gate of the second FET are electrically coupled to contact areas at a second side of the one semiconductor die opposite to the first side, respectively. The contact areas of the other one of source/drain of the first FET, of the gate of the first FET, of the other one of source/drain of the second FET and of the gate of the second FET are electrically separated from each other, respectively.Type: ApplicationFiled: January 27, 2009Publication date: July 29, 2010Applicant: INFINEON TECHNOLOGIES AUSTRIA AGInventors: Oliver Haeberlen, Walter Rieger, Lutz Goergens, Martin Poelzl, Johannes Schoiswohl, Joachim Krumrey