Abstract: A system for recognition of objects in a game, the system has a table with playing board for pucks on which the game is played, and reference markings distributed across the playing board that are used together with corner of the playing board in a surface mapping process. At least one area scan camera acquires images of the playing table during a game and reads fiducial marker of pucks that have the fiducial markers. The at least one area scan camera is arranged to cover the playing board and the reference markings. A processing unit processes the images acquired by the at least one camera.

Abstract: In processors, notably digital signal processors, it is often necessary to form the sum of products of a concatenation of data word pairs, for example for correlation or convolution operations, in which the one data word of each pair can assume only one of the two values +1 or -1. In accordance with the invention, in that case instead of forming a product in a multiplier, the one data word of each pair is applied to an add/subtract device in order to control the function thereof in respect of addition or subtraction; one input of the add/subtract unit then receives the other data words of the data word pairs, and the other input is connected to the output of the accumulator register. Thus, a complex multiplier device is saved or, should such a device be present anyway, it will not be used so that the power loss of the processor is reduced.

Abstract: Digital signal processing often requires the fast summing of a chain of products. Known signal processors often use two separate dam buses via which the values to be multiplied are supplied in parallel, it being assumed that these values originate from different sources, for example from different memories. Because a product of two binary numbers has double the number of positions, therefore, an adder having double the word width is also used. In order to reduce this substantial expenditure at the expense of only a slight reduction in speed, an adder is provided having only the single word width and to process the most-significant and least-significant bits of the product during two successive clock periods. The values to be multiplied can then be supplied successively.