Abstract: A circuit receives a clock signal, a data word which is emitted from a control device and has information about a read or write access to the circuit, and an enable signal which is at a predetermined value during the transmission of the data word. A determination unit uses the number of clock cycles of the clock signal during which the enable signal is at the predetermined value to determine the digital interface standard on which the data word transmitted during these clock cycles is based.

Abstract: The invention includes a memory device with a register device to which an output of a multiplexer is connected. The input of the multiplexer is connected to a buffer store. In addition, the memory device includes a synchronization circuit having a control output connected to a control input of the multiplexer. A clock signal output of the synchronization circuit is connected to the clock input of the register device. The synchronization circuit generates and outputs a clock signal to the clock signal output derived from a time profile for a signal on a state input and from a signal on a second clock input. In this way, a data word to be stored in the register device is synchronized to a clock signal on the second clock input, so that data errors are avoided during transfer.