Patents by Inventor Johannes Van Meer
Johannes Van Meer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11378893Abstract: A lithographic apparatus is described having a liquid supply system configured to at least partly fill a space between a projection system of the lithographic apparatus and a substrate with liquid, a barrier member arranged to substantially contain the liquid within the space, and a heater.Type: GrantFiled: November 13, 2020Date of Patent: July 5, 2022Assignee: ASML NETHERLANDS B.V.Inventors: Theodorus Petrus Maria Cadee, Johannes Henricus Wilhelmus Jacobs, Nicolaas Ten Kate, Erik Roelof Loopstra, Aschwin Lodewijk Hendricus Johannes Van Meer, Jeroen Johannes Sophia Maria Mertens, Christianus Gerardus Maria De Mol, Marcel Johannus Elisabeth Hubertus Muitjens, Antonius Johannus Van Der Net, Joost Jeroen Ottens, Johannes Anna Quaedackers, Maria Elisabeth Reuhman-Huisken, Marco Koert Stavenga, Patricius Aloysius Jacobus Tinnemans, Martinus Cornelis Maria Verhagen, Jacobus Johannus Leonardus Hendricus Verspay, Frederik Eduard De Jong, Koen Goorman, Boris Menchtchikov, Herman Boom, Stoyan Nihtianov, Richard Moerman, Martin Frans Pierre Smeets, Bart Leonard Peter Schoondermark, Franciscus Johannes Joseph Janssen, Michel Riepen
-
Patent number: 11217491Abstract: Methods herein may include forming a gate dielectric within a set of trenches in a stack of layers. A first work function (WF) metal may be formed atop the gate dielectric, and a capping layer may be formed over the first WF metal using an angled ion implant deposition, the capping layer extending across the trenches.Type: GrantFiled: July 18, 2019Date of Patent: January 4, 2022Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Min Gyu Sung, Naushad K. Variam, Sony Varghese, Johannes Van Meer, Jae Young Lee
-
Patent number: 10971403Abstract: A method for forming a semiconductor device. The method may include providing a transistor structure, where the transistor structure includes a fin array, the fin array including a plurality of semiconductor fins, disposed on a substrate. A liner may be disposed on the plurality of semiconductor fins. The method may include directing first angled ions to the fin array, wherein the liner is removed in an upper portion of the plurality of semiconductor fins, and wherein the liner remains in a lower portion of the at least one of the plurality of semiconductor fins, and wherein the upper portion comprises an active fin region to form a transistor device.Type: GrantFiled: December 13, 2019Date of Patent: April 6, 2021Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Min Gyu Sung, Naushad K. Variam, Sony Varghese, Johannes Van Meer, Jae Young Lee
-
Publication number: 20210063898Abstract: A lithographic apparatus is described having a liquid supply system configured to at least partly fill a space between a projection system of the lithographic apparatus and a substrate with liquid, a barrier member arranged to substantially contain the liquid within the space, and a heater.Type: ApplicationFiled: November 13, 2020Publication date: March 4, 2021Applicant: ASML NETHERLANDS B.V.Inventors: Theodorus Petrus Maria CADEE, Johannes Henricus Wilhelmus JACOBS, Nicolaas TEN KATE, Erik Roelof LOOPSTRA, Aschwin Lodewijk Hendricus Johannes VAN MEER, Jeroen Johannes Sophia Maria MERTENS, Christianus Gerardus Maria DE MOL, Marcel Johannus Elisabeth Hubertus MUITJENS, Antonius Johannus VAN DER NET, Joost Jeroen OTTENS, Johannes Anna QUAEDACKERS, Maria Elisabeth REUHMAN-HUISKEN, Marco Koert STAVENGA, Patricius Aloysius Jacobus TINNEMANS, Martinus Cornelis Maria VERHAGEN, Jacobus Johannus Leonardus Hendricus VERSPAY, Frederik Eduard DE JONG, Koen GOORMAN, Boris MENCHTCHIKOV, Herman BOOM, Stoyan NIHTIANOV, Richard MOERMAN, Martin Frans Pierre SMEETS, Bart Leonard Peter SCHOONDERMARK, Franciscus Johannes Joseph JANSSEN, Michel RIEPEN
-
Patent number: 10838310Abstract: A lithographic apparatus is described having a liquid supply system configured to at least partly fill a space between a projection system of the lithographic apparatus and a substrate with liquid, a barrier member arranged to substantially contain the liquid within the space, and a heater.Type: GrantFiled: April 5, 2019Date of Patent: November 17, 2020Assignee: ASML NETHERLANDS B.V.Inventors: Theodorus Petrus Maria Cadee, Johannes Henricus Wilhelmus Jacobs, Nicolaas Ten Kate, Erik Roelof Loopstra, Aschwin Lodewijk Hendricus Johannes Van Meer, Jeroen Johannes Sophia Maria Mertens, Christianus Gerardus Maria De Mol, Marcel Johannus Elisabeth Hubertus Muitjens, Antonius Johannus Van Der Net, Joost Jeroen Ottens, Johannes Anna Quaedackers, Maria Elisabeth Reuhman-Huisken, Marco Koert Stavenga, Patricius Aloysius Jacobus Tinnemans, Martinus Cornelis Maria Verhagen, Jacobus Johannus Leonardus Hendricus Verspay, Frederik Eduard De Jong, Koen Goorman, Boris Menchtchikov, Herman Boom, Stoyan Nihtianov, Richard Moerman, Martin Frans Pierre Smeets, Bart Leonard Peter Schoondermark, Franciscus Johannes Joseph Janssen, Michel Riepen
-
Patent number: 10720357Abstract: A method of forming a semiconductor device. The method may include providing a device structure, where the device structure comprises a masked portion and a cut portion. The masked portion may comprise a mask covering at least one semiconductor fin of a fin array, and the cut portion may comprise a trench, where the trench exposes a semiconductor fin region of the fin array. The method may further include providing an exposure of the trench to oxidizing ions, the oxidizing ions to transform a semiconductor material into an oxide.Type: GrantFiled: March 1, 2018Date of Patent: July 21, 2020Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Min Gyu Sung, Naushad K Variam, Sony Varghese, Johannes Van Meer, Jae Young Lee, Jun Lee
-
Patent number: 10692775Abstract: Disclosed are methods of forming a semiconductor device, such as a finFET device. One non-limiting method may include providing a semiconductor device including a substrate and a plurality of fins extending from the substrate, and forming a source trench isolation (STI) material over the semiconductor device. The method may further include recessing the STI material to reveal an upper portion of the plurality of fins, implanting the semiconductor device, and forming a capping layer over the plurality of fins and the STI material. The method may further include removing a first fin section of the plurality of fins and a first portion of the capping layer, wherein a second fin section of the plurality of fins remains following removal of the first fin section.Type: GrantFiled: November 9, 2018Date of Patent: June 23, 2020Assignee: Applied Materials, Inc.Inventors: Min Gyu Sung, Jae Young Lee, Johannes Van Meer, Sony Varghese, Naushad K. Variam
-
Patent number: 10685865Abstract: A method of forming a semiconductor device may include providing a semiconductor device structure. The semiconductor device structure may include semiconductor fins pitched at a fin pitch on a substrate and a mask, disposed over the semiconductor fins, the mask defining a plurality of openings. The semiconductor device structure may further include an isolation oxide disposed on the substrate, between the semiconductor fins. The method may further include directing angled ions into the at least one of the plurality of openings. The angled ions may form at least one trench between at least one pair of the semiconductor fins, in the substrate below the isolation oxide between the at least one pair of the semiconductor fins. Furthermore, a width within the substrate of the at least one trench is greater than a minimum fin pitch and greater than a width of the at least one trench above the substrate.Type: GrantFiled: July 17, 2018Date of Patent: June 16, 2020Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Min Gyu Sung, Sony Varghese, Johannes Van Meer, John Hautala
-
Patent number: 10686033Abstract: Disclosed are methods of forming a semiconductor device, such as a finFET device. One non-limiting method may include providing a semiconductor device including a substrate and a plurality of fins extending from the substrate, and forming a source trench isolation (STI) material over the semiconductor device. The method may further include performing a fin cut by removing a first fin section of the plurality of fins and a first portion of the STI material, and forming a second STI material over a second fin section of the plurality of fins, wherein the second fin section is left remaining following removal of the first fin section. The method may further include recessing the STI material and the second STI material, forming a spin-on-carbon (SOC) layer over the semiconductor device, and implanting the STI material and the second STI material through the SOC layer.Type: GrantFiled: November 9, 2018Date of Patent: June 16, 2020Assignee: Applied Materials, Inc.Inventors: Min Gyu Sung, Jae Young Lee, Johannes Van Meer, Sony Varghese, Naushad K. Variam
-
Publication number: 20200152735Abstract: Disclosed are methods of forming a semiconductor device, such as a finFET device. One non-limiting method may include providing a semiconductor device including a substrate and a plurality of fins extending from the substrate, and forming a source trench isolation (STI) material over the semiconductor device. The method may further include performing a fin cut by removing a first fin section of the plurality of fins and a first portion of the STI material, and forming a second STI material over a second fin section of the plurality of fins, wherein the second fin section is left remaining following removal of the first fin section. The method may further include recessing the STI material and the second STI material, forming a spin-on-carbon (SOC) layer over the semiconductor device, and implanting the STI material and the second STI material through the SOC layer.Type: ApplicationFiled: November 9, 2018Publication date: May 14, 2020Applicant: APPLIED Materials, Inc.Inventors: Min Gyu Sung, Jae Young Lee, Johannes Van Meer, Sony Varghese, Naushad K. Variam
-
Publication number: 20200152519Abstract: Disclosed are methods of forming a semiconductor device, such as a finFET device. One non-limiting method may include providing a semiconductor device including a substrate and a plurality of fins extending from the substrate, and forming a source trench isolation (STI) material over the semiconductor device. The method may further include recessing the STI material to reveal an upper portion of the plurality of fins, implanting the semiconductor device, and forming a capping layer over the plurality of fins and the STI material. The method may further include removing a first fin section of the plurality of fins and a first portion of the capping layer, wherein a second fin section of the plurality of fins remains following removal of the first fin section.Type: ApplicationFiled: November 9, 2018Publication date: May 14, 2020Applicant: APPLIED Materials, Inc.Inventors: Min Gyu Sung, Jae Young Lee, Johannes Van Meer, Sony Varghese, Naushad K. Variam
-
Publication number: 20200135573Abstract: A method for forming a semiconductor device. The method may include providing a transistor structure, where the transistor structure includes a fin array, the fin array including a plurality of semiconductor fins, disposed on a substrate. A liner may be disposed on the plurality of semiconductor fins. The method may include directing first angled ions to the fin array, wherein the liner is removed in an upper portion of the plurality of semiconductor fins, and wherein the liner remains in a lower portion of the at least one of the plurality of semiconductor fins, and wherein the upper portion comprises an active fin region to form a transistor device.Type: ApplicationFiled: December 13, 2019Publication date: April 30, 2020Applicant: Varian Semiconductor Equipment Associates, Inc.Inventors: Min Gyu Sung, Naushad K. Variam, Sony Varghese, Johannes Van Meer, Jae Young Lee
-
Publication number: 20200135928Abstract: A method of forming a semiconductor device may include providing a semiconductor device structure. The semiconductor device structure may include semiconductor fins pitched at a fin pitch on a substrate. The semiconductor device structure may include an isolation oxide layer on the substrate and between the semiconductor fins and a mask. The mask may be disposed over the isolation oxide layer and the mask may define at least one opening. The method may further comprise directing hot ions into the at least one opening, to implant hot ions in a volume of isolation oxide in the isolation oxide layer. The volume may be adjacent to at least one of the semiconductor fins.Type: ApplicationFiled: October 30, 2018Publication date: April 30, 2020Applicant: APPLIED Materials, Inc.Inventors: Min Gyu Sung, Johannes Van Meer
-
Patent number: 10629741Abstract: A method of forming a semiconductor device may include providing a semiconductor device structure. The semiconductor device structure may include semiconductor fins pitched at a fin pitch on a substrate. The semiconductor device structure may include an isolation oxide layer on the substrate and between the semiconductor fins and a mask. The mask may be disposed over the isolation oxide layer and the mask may define at least one opening. The method may further comprise directing hot ions into the at least one opening, to implant hot ions in a volume of isolation oxide in the isolation oxide layer. The volume may be adjacent to at least one of the semiconductor fins.Type: GrantFiled: October 30, 2018Date of Patent: April 21, 2020Assignee: Applied Materials, Inc.Inventors: Min Gyu Sung, Johannes Van Meer
-
Patent number: 10510610Abstract: A method for forming a semiconductor device. The method may include providing a transistor structure, where the transistor structure includes a fin array, the fin array including a plurality of semiconductor fins, disposed on a substrate. A liner may be disposed on the plurality of semiconductor fins. The method may include directing first angled ions to the fin array, wherein the liner is removed in an upper portion of the plurality of semiconductor fins, and wherein the liner remains in a lower portion of the at least one of the plurality of semiconductor fins, and wherein the upper portion comprises an active fin region to form a transistor device.Type: GrantFiled: March 28, 2018Date of Patent: December 17, 2019Assignee: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.Inventors: Min Gyu Sung, Naushad K. Variam, Sony Varghese, Johannes Van Meer, Jae Young Lee
-
Patent number: 10510870Abstract: A method for forming a semiconductor device may include providing a transistor structure. The transistor structure may include a set of semiconductor fins and a set of gate structures, disposed on the set of semiconductor fins, wherein an isolation layer is disposed between the set of semiconductor fins and between the set of gate structures. The method may include implanting ions into an exposed area of the isolation layer, wherein an altered portion of the isolation layer is formed in the exposed area, wherein an altered region of the set of semiconductor fins is formed in an exposed portion of the set of semiconductor fins. The altered portion of the isolation layer may have a first etch rate, wherein an unaltered portion of the isolation layer, not exposed to the ions, has a second etch rate, greater than the first etch rate.Type: GrantFiled: February 21, 2018Date of Patent: December 17, 2019Assignee: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.Inventors: Min Gyu Sung, Sony Varghese, Jae Young Lee, Johannes Van Meer
-
Publication number: 20190341315Abstract: Methods herein may include forming a gate dielectric within a set of trenches in a stack of layers. A first work function (WF) metal may be formed atop the gate dielectric, and a capping layer may be formed over the first WF metal using an angled ion implant deposition, the capping layer extending across the trenches.Type: ApplicationFiled: July 18, 2019Publication date: November 7, 2019Applicant: Varian Semiconductor Equipment Associates, Inc.Inventors: Min Gyu Sung, Naushad K. Variam, Sony Varghese, Johannes Van Meer, Jae Young Lee
-
Publication number: 20190304841Abstract: A method for forming a semiconductor device. The method may include providing a transistor structure, where the transistor structure includes a fin array, the fin array including a plurality of semiconductor fins, disposed on a substrate. A liner may be disposed on the plurality of semiconductor fins. The method may include directing first angled ions to the fin array, wherein the liner is removed in an upper portion of the plurality of semiconductor fins, and wherein the liner remains in a lower portion of the at least one of the plurality of semiconductor fins, and wherein the upper portion comprises an active fin region to form a transistor device.Type: ApplicationFiled: March 28, 2018Publication date: October 3, 2019Applicant: Varian Semiconductor Equipment Associates, Inc.Inventors: Min Gyu Sung, Naushad K. Variam, Sony Varghese, Johannes Van Meer, Jae Young Lee
-
Publication number: 20190273011Abstract: A method of forming a semiconductor device. The method may include providing a device structure, where the device structure comprises a masked portion and a cut portion. The masked portion may comprise a mask covering at least one semiconductor fin of a fin array, and the cut portion may comprise a trench, where the trench exposes a semiconductor fin region of the fin array. The method may further include providing an exposure of the trench to oxidizing ions, the oxidizing ions to transform a semiconductor material into an oxide.Type: ApplicationFiled: March 1, 2018Publication date: September 5, 2019Applicant: Varian Semiconductor Equipment Associates, Inc.Inventors: Min Gyu Sung, Naushad K. Variam, Sony Varghese, Johannes Van Meer, Jae Young Lee, Jun Lee
-
Patent number: 10403552Abstract: Methods herein may include forming trenches in a stack of layers atop a substrate, and forming a gate dielectric within the trenches. Methods may further include forming a first work function (WF) metal atop the gate dielectric, and forming a capping layer over the first WF metal using an angled ion implant deposition, the capping layer extending across the trenches. The first WF metal may be removed from just a first trench of the trenches, and a second WF metal is then formed over the stack of layers, wherein the second WF metal is formed atop the gate dielectric within the first trench. An angled ion etch may then be performed to recess the gate dielectric and the second WF metal within the first trench, and to recess the gate dielectric and the first WF metal within a second trench. A gate metal may then be formed within the trenches.Type: GrantFiled: April 2, 2018Date of Patent: September 3, 2019Assignee: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.Inventors: Min Gyu Sung, Naushad K. Variam, Sony Varghese, Johannes Van Meer, Jae Young Lee