Abstract: A semiconductor body (10) has at one major surface (15) a step (14) defining a device area (13) of the semiconductor body above a buried region (12) provided within the semiconductor body (10). A protective insulating layer (24) is provided on a side wall (14a) of the step (14) and an insulating region (22) on an area (15a) of the one major surface adjoining the side wall (14a) of the step. Silicon is deposited over the one surface (15) with the anti-oxidation layer (24) on the side wall (14a) of the step (14) to define over the area (15a) of the one surface (15) an intermediate silicon region (23c) which is isolated from the side wall (14a) of the step and which leaves a window area (14'a) of the side wall (14a) exposed. The protective insulating layer (24a) is then removed from the window area (14'a) of the side wall (14a).

Abstract: A method of manufacturing a semiconductor device having a monocrystalline silicon region (3) comprising a first zone (9) and an adjacent second zone (10) and laterally enclosed by a sunken oxide layer (4) and by an overlying highly doped polycrystalline silicon layer (5). The silicon layer (5) is laterally separated by an oxide layer (6) from the silicon region (3) and adjoins the first zone (9) on a narrow edge portion of the upper surface of the region (3), this zone being of the same conductivity type as the silicon layer (5). The second zone (10) is provided with an electrode layer (11). According to the invention, the silicon layer (5) is separated from the electrode layer (11) by an oxide strip (12A) formed in a self-aligned manner and at least one doped connection zone (13) having a width determined by said oxide strip (12A) is situated between said first and said second zones and located below said oxide strip (12A).

Abstract: A device area (16) is defined in a semiconductor body (10) by forming at one major surface (12, 12a) of the body a step (11) having a side wall (11a) and top surface (11b) bounding the device area 16. A silicon layer (13) is deposited so as to cover the side wall (11a) and top surface (11b) of the step and an adjoining lower surface area (12c). Dopant impurities are introduced so that the side wall silicon region (13a) is shielded from the dopant impurities and the undoped side wall silicon region (13a) is later removed by selective etching. The silicon region (13c) on the lower surface area (12a) adjoining the step (11) is masked and the silicon region (13a) on the top surface (11b) at the step (11) removed to leave the doped silicon region (13c) on the one major surface (12a) for contacting a device region (29), for example the base region of a transistor, of the device area.

Abstract: A semiconductor device having a monocrystalline silicon region (3) comprising a first zone (9) and an adjacent second zone (10) and laterally enclosed by a sunken oxide layer (4) and by an overlying highly doped polycrystalline silicon layer (5). The silicon layer (5) is laterally separated by an oxide layer (6) from the silicon region (3) and adjoins the first zone (9) on a narrow edge portion of the upper surface of the region (3), this zone being of the same conductivity type as the silicon layer (5). The second zone (10) is provided with an electrode layer (11). According to the invention, the silicon layer (5) is separated from the electrode layer (11) by an oxide strip (12A) formed in a self-aligned manner and at least one doped connection zone (13) having a width determined by the oxide strip (12A) is situated between the first and the second zones and located below the oxide strip (12A). The invention further relates to a method of manufacturing this device.

Abstract: A semiconductor device comprising a first region, which is laterally bounded by a second region comprising a countersunk oxide layer and a highly doped polycrystalline silicon layer, which is disposed thereon and is covered by an oxide layer partly countersunk into it. The side edge of the polysilicon layer adjoins a contact zone, which is obtained by diffusion therefrom and is connected via a current path to a zone of a semiconductor circuit element. The upper side of the polysilicon layer is located at a higher level than that of the first region and the contact zone is connected to the said zone of the semiconductor circuit element via an intermediate region located in the first region below the second oxide layer and having a lower doping than the contact zone.