Abstract: Parallel-series converter having a plurality of parallel inputs and comprising a combining arrangement having a plurality of inputs equal in number to the plurality of parallel inputs of the parallel-series converter, and a series output, each parallel input being connected via the series arrangement of a terminating impedance and a transmission line to a respective one of the inputs of the combining arrangement, the delay times of the individual transmission lines having respective different magnitudes according to an arithmetical progression, the junction between each terminating impedance and the associated transmission line being connected to a short-circuited transmission line having a length .lambda./2, where .lambda.

Abstract: Digital transmission system comprising block code conversion supervisory means, which comprises a parity detector to which both the word to be encoded and the encoded word are applied and which further comprises means for detecting and inverting the rules of dual parity depending on the translation code used.