Patents by Inventor Johji Nishio
Johji Nishio has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11973116Abstract: According to one embodiment, a semiconductor device includes a silicon carbide member. The silicon carbide member includes an operating region including at least one of a diode or a transistor, and a first element region including at least one element selected from the group consisting of Ar, V, Al and B. The first element region includes a first region and a second region. A first direction from the first region toward the second region is along a [1-100] direction of the silicon carbide member. The operating region is between the first region and the second region in the first direction. The first element region does not include a region overlapping the operating region in a second direction along a [11-20] direction of the silicon carbide member. Or the first element region includes a third region overlapping the operating region in the second direction.Type: GrantFiled: December 9, 2021Date of Patent: April 30, 2024Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Johji Nishio, Chiharu Ota
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Publication number: 20240072119Abstract: According to one embodiment, a semiconductor device includes a silicon carbide member, a first member, a first layer, and a second layer. The silicon carbide member includes a first region. The first member includes silicon and oxygen. The first layer is provided between the first region and the first member. The first layer includes a bond between silicon and nitrogen. The second layer is provided between the first layer and the first member. The second layer includes a bond between silicon and oxygen and a bond between silicon and nitrogen.Type: ApplicationFiled: February 16, 2023Publication date: February 29, 2024Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yukio NAKABAYASHI, Tatsuo SHIMIZU, Toshihide ITO, Chiharu OTA, Johji NISHIO
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Patent number: 11848211Abstract: A semiconductor device according to an embodiment includes: a silicon carbide layer; a silicon oxide layer; and a region disposed between the silicon carbide layer and the silicon oxide layer and having a nitrogen concentration equal to or more than 1×1021 cm?3. A nitrogen concentration distribution in the silicon carbide layer, the silicon oxide layer, and the region have a peak in the region, a nitrogen concentration at a first position 1 nm away from the peak to the side of the silicon oxide layer is equal to or less than 1×1018 cm?3 and a carbon concentration at the first position is equal to or less than 1×1018 cm?3, and a nitrogen concentration at a second position 1 nm away from the peak to the side of the silicon carbide layer is equal to or less than 1×1018 cm?3.Type: GrantFiled: February 21, 2023Date of Patent: December 19, 2023Assignee: Kabushiki Kaisha ToshibaInventors: Tatsuo Shimizu, Yukio Nakabayashi, Johji Nishio, Chiharu Ota, Toshihide Ito
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Publication number: 20230387216Abstract: A semiconductor device according to an embodiment includes: a silicon carbide layer; a silicon oxide layer; and a region disposed between the silicon carbide layer and the silicon oxide layer and having a nitrogen concentration equal to or more than 1×1021 cm?3. Nitrogen concentration distribution in the silicon carbide layer, the silicon oxide layer, and the region have a peak in the region, a nitrogen concentration at a position 1 nm away from the peak to the side of the silicon oxide layer is equal to or less than 1×1018 cm?3, and a carbon concentration at the position is equal to or less than 1×1018 cm?3.Type: ApplicationFiled: August 1, 2023Publication date: November 30, 2023Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Tatsuo SHIMIZU, Yukio NAKABAYASHI, Johji NISHIO, Chiharu OTA, Toshihide ITO
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Patent number: 11764269Abstract: This semiconductor device according to an embodiment includes: a silicon carbide layer; a gate electrode; a silicon oxide layer between the silicon carbide layer and the gate electrode; and a region between the silicon carbide layer and the silicon oxide layer and having a nitrogen concentration not less than 1×1021 cm?3. A nitrogen concentration distribution in the silicon carbide layer, the silicon oxide layer, and the region has its peak in the region, and a state density Z1/2 in a portion is not more than 1×1011 cm?3. The portion is within 100 nm from the silicon oxide layer toward the silicon carbide layer. A nitrogen concentration and a carbon concentration in a position 1 nm from the peak toward the silicon oxide layer is not more than 1×1018 cm?3, and a nitrogen concentration in a position 1 nm from the peak toward the silicon carbide layer is not more than 1×1018 cm?3.Type: GrantFiled: September 2, 2022Date of Patent: September 19, 2023Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Tatsuo Shimizu, Yukio Nakabayashi, Johji Nishio, Chiharu Ota, Toshihide Ito
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Patent number: 11764059Abstract: According to one embodiment, a method for manufacturing a substrate is disclosed. The method can include preparing a structure body. The structure body includes a first semiconductor member and a second semiconductor member. The first semiconductor member includes silicon carbide including a first element. The second semiconductor member includes silicon carbide including a second element. The first element includes at least one selected from a first group consisting of N, P, and As. The second element includes at least one selected from a second group consisting of B, Al, and Ga. The method can include forming a hole that extends through the second semiconductor member and reaches the first semiconductor member. In addition, the method can include forming a third semiconductor member in the hole. The third semiconductor member includes silicon carbide including a third element. The third element includes at least one selected from the first group.Type: GrantFiled: September 8, 2020Date of Patent: September 19, 2023Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Johji Nishio, Tatsuo Shimizu
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Patent number: 11764270Abstract: A semiconductor device according to an embodiment includes: a silicon carbide layer; a silicon oxide layer; and a region disposed between the silicon carbide layer and the silicon oxide layer and having a nitrogen concentration equal to or more than 1×1021 cm?3. Nitrogen concentration distribution in the silicon carbide layer, the silicon oxide layer, and the region have a peak in the region, a nitrogen concentration at a position 1 nm away from the peak to the side of the silicon oxide layer is equal to or less than 1×1018 cm?3, and a carbon concentration at the position is equal to or less than 1×1018 cm?3.Type: GrantFiled: August 13, 2020Date of Patent: September 19, 2023Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Tatsuo Shimizu, Yukio Nakabayashi, Johji Nishio, Chiharu Ota, Toshihide Ito
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Publication number: 20230207321Abstract: A semiconductor device according to an embodiment includes: a silicon carbide layer; a silicon oxide layer; and a region disposed between the silicon carbide layer and the silicon oxide layer and having a nitrogen concentration equal to or more than 1 × 1021 cm-3. A nitrogen concentration distribution in the silicon carbide layer, the silicon oxide layer, and the region have a peak in the region, a nitrogen concentration at a first position 1 nm away from the peak to the side of the silicon oxide layer is equal to or less than 1 × 1018 cm-3 and a carbon concentration at the first position is equal to or less than 1 × 1018 cm-3, and a nitrogen concentration at a second position 1 nm away from the peak to the side of the silicon carbide layer is equal to or less than 1 × 1018 cm-3.Type: ApplicationFiled: February 21, 2023Publication date: June 29, 2023Applicant: Kabushiki Kaisha ToshibaInventors: Tatsuo SHIMIZU, Yukio NAKABAYASHI, Johji NISHIO, Chiharu OTA, Toshihide ITO
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Publication number: 20230197790Abstract: A method for manufacturing a semiconductor device of an embodiment includes performing first ion implantation of implanting aluminum (Al) into a silicon carbide layer in a first projected range and a first dose amount, performing second ion implantation of implanting carbon (C) into the silicon carbide layer in a second projected range and a second dose amount which is a dose amount equal to or more than 10 times the first dose amount, performing a first heat treatment of 1600° C. or more, performing an oxidation treatment of oxidizing the silicon carbide layer, performing an etching process of etching the silicon carbide layer in an atmosphere containing a hydrogen gas, forming a silicon oxide film on the silicon carbide layer, and forming a gate electrode on the silicon oxide film.Type: ApplicationFiled: August 30, 2022Publication date: June 22, 2023Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Tatsuo SHIMIZU, Yukio NAKABAYASHI, Toshihide ITO, Chiharu OTA, Johji NISHIO
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Publication number: 20230107057Abstract: According to one embodiment, a wafer includes a base body including a first surface, and a crystal layer provided on the first surface. The crystal layer includes first stacking faults and one or second stacking faults. One of the first stacking faults includes a first long side, a first short side, and a first hypotenuse. A position of the first long side in a first direction from the base body to the crystal layer is between the base body in the first direction and a first corner portion in the first direction. One of the one or the plurality of second stacking faults includes a second long side, a second short side, and a second hypotenuse. A position of a second corner portion in the first direction is between the base body in the first direction and the second long side in the first direction.Type: ApplicationFiled: July 13, 2022Publication date: April 6, 2023Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Johji NISHIO, Chiharu OTA, Tatsuo SHIMIZU, Ryosuke IIJIMA
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Patent number: 11621167Abstract: A semiconductor device according to an embodiment includes: a silicon carbide layer; a silicon oxide layer; and a region disposed between the silicon carbide layer and the silicon oxide layer and having a nitrogen concentration equal to or more than 1×1021 cm?3. A nitrogen concentration distribution in the silicon carbide layer, the silicon oxide layer, and the region have a peak in the region, a nitrogen concentration at a first position 1 nm away from the peak to the side of the silicon oxide layer is equal to or less than 1×1018 cm?3 and a carbon concentration at the first position is equal to or less than 1×1018 cm?3, and a nitrogen concentration at a second position 1 nm away from the peak to the side of the silicon carbide layer is equal to or less than 1×1018 cm?3.Type: GrantFiled: January 5, 2022Date of Patent: April 4, 2023Assignee: Kabushiki Kaisha ToshibaInventors: Tatsuo Shimizu, Yukio Nakabayashi, Johji Nishio, Chiharu Ota, Toshihide Ito
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Publication number: 20230084127Abstract: A semiconductor device manufacturing method of embodiments includes: forming a silicon oxide film on a surface of a silicon carbide layer; performing a first heat treatment in an atmosphere containing nitrogen gas at a temperature equal to or more than 1200° C. and equal to or less than 1600° C.; and performing a second heat treatment in an atmosphere containing nitrogen oxide gas at a temperature equal to or more than 750° C. and equal to or less than 1050° C.Type: ApplicationFiled: March 7, 2022Publication date: March 16, 2023Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Tatsuo SHIMIZU, Yukio NAKABAYASHI, Toshihide ITO, Chiharu OTA, Shigeto FUKATSU, Johji NISHIO, Ryosuke IIJIMA
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Publication number: 20230064469Abstract: According to one embodiment, a wafer includes a substrate and a crystal layer. The substrate includes a plurality of SiC regions including SiC and an inter-SiC region including Si provided between the SiC regions. The crystal layer includes a first layer, and a first intermediate layer provided between the substrate and the first layer in a first direction. The first layer includes SiC and nitrogen. The first intermediate layer includes SiC and nitrogen. A second concentration of nitrogen in the first intermediate layer is higher than a first concentration of nitrogen in the first layer.Type: ApplicationFiled: February 2, 2022Publication date: March 2, 2023Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Mitsuhiro KUSHIBE, Johji NISHIO, Ryosuke IIJIMA, Tatsuo SHIMIZU, Chiharu OTA, Shoko SUYAMA
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Patent number: 11563090Abstract: According to an embodiment of the invention, a semiconductor device includes a base body that includes silicon carbide, a first semiconductor member that includes silicon carbide and is of a first conductivity type, and a second semiconductor member that includes silicon carbide and is of a second conductivity type. A first direction from the base body toward the first semiconductor member is along a [0001] direction of the base body. The second semiconductor member includes a first region, a second region, and a third region. The first semiconductor member includes a fourth region. A second direction from the first region toward the second region is along a [1-100] direction of the base body. The fourth region is between the first region and the second region in the second direction. A third direction from the fourth region toward the third region is along a [11-20] direction of the base body.Type: GrantFiled: September 8, 2020Date of Patent: January 24, 2023Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Johji Nishio, Tatsuo Shimizu
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Publication number: 20220416030Abstract: This semiconductor device according to an embodiment includes: a silicon carbide layer; a gate electrode; a silicon oxide layer between the silicon carbide layer and the gate electrode; and a region between the silicon carbide layer and the silicon oxide layer and having a nitrogen concentration not less than 1×1021 cm?3. A nitrogen concentration distribution in the silicon carbide layer, the silicon oxide layer, and the region has its peak in the region, and a state density Z1/2 in a portion is not more than 1×1011 cm?3. The portion is within 100 nm from the silicon oxide layer toward the silicon carbide layer. A nitrogen concentration and a carbon concentration in a position 1 nm from the peak toward the silicon oxide layer is not more than 1×1018 cm?3, and a nitrogen concentration in a position 1 nm from the peak toward the silicon carbide layer is not more than 1×1018 cm?3.Type: ApplicationFiled: September 2, 2022Publication date: December 29, 2022Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Tatsuo SHIMIZU, Yukio NAKABAYASHI, Johji NISHIO, Chiharu OTA, Toshihide ITO
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Publication number: 20220359665Abstract: According to one embodiment, a semiconductor device includes a silicon carbide member. The silicon carbide member includes an operating region including at least one of a diode or a transistor, and a first element region including at least one element selected from the group consisting of Ar, V, Al and B. The first element region includes a first region and a second region. A first direction from the first region toward the second region is along a [1-100] direction of the silicon carbide member. The operating region is between the first region and the second region in the first direction. The first element region does not include a region overlapping the operating region in a second direction along a [11-20] direction of the silicon carbide member. Or the first element region includes a third region overlapping the operating region in the second direction.Type: ApplicationFiled: December 9, 2021Publication date: November 10, 2022Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Johji NISHIO, Chiharu OTA
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Patent number: 11469301Abstract: This semiconductor device according to an embodiment includes: a silicon carbide layer; a gate electrode; a silicon oxide layer between the silicon carbide layer and the gate electrode; and a region between the silicon carbide layer and the silicon oxide layer and having a nitrogen concentration not less than 1×1021 cm?3. A nitrogen concentration distribution in the silicon carbide layer, the silicon oxide layer, and the region has its peak in the region, and a state density Z1/2 in a portion is not more than 1×1011 cm?3. The portion is within 100 nm from the silicon oxide layer toward the silicon carbide layer. A nitrogen concentration and a carbon concentration in a position 1 nm from the peak toward the silicon oxide layer is not more than 1×1018 cm?3, and a nitrogen concentration in a position 1 nm from the peak toward the silicon carbide layer is not more than 1×1018 cm?3.Type: GrantFiled: February 16, 2021Date of Patent: October 11, 2022Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Tatsuo Shimizu, Yukio Nakabayashi, Johji Nishio, Chiharu Ota, Toshihide Ito
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Patent number: 11450745Abstract: A semiconductor device according to embodiments includes a p-type SiC region, a gate insulating film disposed on the p-type SiC region, and a gate electrode disposed on the gate insulating film and including a p-type impurity and 3C—SiC.Type: GrantFiled: February 5, 2020Date of Patent: September 20, 2022Assignee: Kabushiki Kaisha ToshibaInventors: Tatsuo Shimizu, Johji Nishio, Takashi Shinohe
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Patent number: 11443946Abstract: According to one embodiment, a method for manufacturing a silicon carbide base body is disclosed. The method can include preparing a first base body including silicon carbide. The first base body includes a first base body surface tilted with respect to a (0001) plane of the first base body. A first line segment where the first base body surface and the (0001) plane of the first base body intersect is along a [11-20] direction of the first base body. The method can include forming a first layer at the first base body surface. The first layer includes silicon carbide. The method can include removing a portion of the first layer. The first-layer surface is tilted with respect to a (0001) plane of the first layer. A second line segment where the first-layer surface and the (0001) plane of the first layer intersect is along a [?1100] direction.Type: GrantFiled: August 27, 2020Date of Patent: September 13, 2022Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Johji Nishio, Chiharu Ota
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Patent number: 11424326Abstract: According to one embodiment, a semiconductor device includes a silicon carbide member, first, second, and third electrodes, and a first insulating member. The silicon carbide member includes first, second, and third silicon carbide regions. The first silicon carbide region includes first, second, third, and fourth partial regions. The third partial region is between the first and second partial regions. The fourth partial region is between the third partial region and the first electrode. The second silicon carbide region includes first and second semiconductor regions. The third silicon carbide region includes third and fourth semiconductor regions. The first insulating member includes first, second, and third insulating regions. The second electrode is electrically connected to the first silicon carbide region. The third and fourth partial regions are between the second and first electrodes. The third electrode is electrically connected to the second silicon carbide region.Type: GrantFiled: January 26, 2021Date of Patent: August 23, 2022Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Yukio Nakabayashi, Tatsuo Shimizu, Toshihide Ito, Chiharu Ota, Johji Nishio