Patents by Inventor John A. Bentley
John A. Bentley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11920814Abstract: A method of controlling an agricultural facility for housing a plurality of animals includes the step of regulating the environment within the agricultural facility with an automated building operational system. An automated thermal event controller is operationally coupled with the automated building operational system and generates a thermal event signal in response to a thermal event in progress, whereby the automated thermal event controller, upon receipt of the thermal event signal indicating that the thermal event is in progress, activates an alarm state. In the alarm state, the automated thermal event controller: sends an alarm signal to a system administrator; places the automated building operational system in a safety-mode condition for a first predetermined time interval; and places the automated building operational system in a normal-mode operational condition after the first predetermined time interval and if a confirmatory signal is not yet then received from the system administrator.Type: GrantFiled: March 24, 2022Date of Patent: March 5, 2024Assignee: PRISM CONTROLS INC.Inventors: Sean Patrick Ryan, Kyle E. Forbush, Nikhil Kailas Shinde, Sylvester John Bentley, Timothy Paul Gess, Eric William Hansen, Douglas S. Powell
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Publication number: 20220316739Abstract: A method of controlling an agricultural facility for housing a plurality of animals includes the step of regulating the environment within the agricultural facility with an automated building operational system. An automated thermal event controller is operationally coupled with the automated building operational system and generates a thermal event signal in response to a thermal event in progress, whereby the automated thermal event controller, upon receipt of the thermal event signal indicating that the thermal event is in progress, activates an alarm state. In the alarm state, the automated thermal event controller: sends an alarm signal to a system administrator; places the automated building operational system in a safety-mode condition for a first predetermined time interval; and places the automated building operational system in a normal-mode operational condition after the first predetermined time interval and if a confirmatory signal is not yet then received from the system administrator.Type: ApplicationFiled: March 24, 2022Publication date: October 6, 2022Applicant: POULTRY MANAGEMENT SYSTEMS, INC.Inventors: Sean Patrick Ryan, Kyle E. Forbush, Nikhil Kailas Shinde, Sylvester John Bentley, Timothy Paul Gess, Eric William Hansen, Douglas S. Powell
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Patent number: 11217533Abstract: A semiconductor device is provided, the semiconductor device comprising a substrate and a first semiconductor fin and a second semiconductor fin disposed over the substrate. The first and second semiconductor fins each having an upper portion and a width. Epitaxial structures are disposed over the upper portions of the first and second semiconductor fins. The upper portions of the first and second semiconductor fins and the epitaxial structures provide an active layer. A metal structure is positioned between the active layer and the substrate. The metal structure extends at least across the widths of the first and second semiconductor fins and a separation distance between the fins. A first isolation material separates the metal structure from the active layer. A second isolation material separates the metal structure from the substrate. A contact electrically connects the metal structure to the epitaxial structures.Type: GrantFiled: February 7, 2020Date of Patent: January 4, 2022Assignee: GLOBALFOUNDRIES U.S. Inc.Inventors: Steven Robert Soss, Steven John Bentley, Julien Frougier
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Publication number: 20210249352Abstract: A semiconductor device is provided, the semiconductor device comprising a substrate and a first semiconductor fin and a second semiconductor fin disposed over the substrate. The first and second semiconductor fins each having an upper portion and a width. Epitaxial structures are disposed over the upper portions of the first and second semiconductor fins. The upper portions of the first and second semiconductor fins and the epitaxial structures provide an active layer. A metal structure is positioned between the active layer and the substrate. The metal structure extends at least across the widths of the first and second semiconductor fins and a separation distance between the fins. A first isolation material separates the metal structure from the active layer. A second isolation material separates the metal structure from the substrate. A contact electrically connects the metal structure to the epitaxial structures.Type: ApplicationFiled: February 7, 2020Publication date: August 12, 2021Inventors: STEVEN ROBERT SOSS, STEVEN JOHN BENTLEY, JULIEN FROUGIER
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Publication number: 20190035566Abstract: A switch conversion apparatus including an interface device, a mounting plate configured to mount to a toggle switch and including at least one aperture for receiving a toggle arm of a toggle switch, and an actuator plate configured to slidably engage the mounting plate and including at least one aperture for receiving and engaging a toggle arm of a toggle switch when engaged by the interface device so as to transition the state of the switch. Other embodiments of a switch conversion apparatus include one or more mechanical, electrical, and/or pneumatic timers.Type: ApplicationFiled: October 4, 2018Publication date: January 31, 2019Applicant: Effortless Systems, LLCInventors: Michael S. Mahle, Mark P. Rau, Craig F. Hofmann, Craig Person, John F. Kasper, Daniel John Bentley, Scott D. Reiner, Christopher J. Lundgren
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Patent number: 10141446Abstract: Formation of a bottom junction in vertical FET devices may include, for instance, providing an intermediate semiconductor structure comprising a semiconductor substrate, a fin disposed on the semiconductor substrate. The fin has a top surface, spaced-apart vertical sides. A mask is disposed over the top surface of the fin, and at least one is disposed over the vertical sides of the fin. Portions of the substrate are removed to define spaced-apart recesses each extending below a respective one of the spacers. Semiconductor material is grown, such as epitaxially grown, in the recesses.Type: GrantFiled: October 25, 2017Date of Patent: November 27, 2018Assignee: GLOBALFOUNDRIES Inc.Inventors: Hiroaki Niimi, Kwan-Yong Lim, Steven John Bentley, Daniel Chanemougame
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Publication number: 20180061993Abstract: Formation of a bottom junction in vertical FET devices may include, for instance, providing an intermediate semiconductor structure comprising a semiconductor substrate, a fin disposed on the semiconductor substrate. The fin has a top surface, spaced-apart vertical sides. A mask is disposed over the top surface of the fin, and at least one is disposed over the vertical sides of the fin. Portions of the substrate are removed to define spaced-apart recesses each extending below a respective one of the spacers. Semiconductor material is grown, such as epitaxially grown, in the recesses.Type: ApplicationFiled: October 25, 2017Publication date: March 1, 2018Applicant: GLOBALFOUNDRIES Inc.Inventors: Hiroaki NIIMI, Kwan-Yong LIM, Steven John BENTLEY, Daniel CHANEMOUGAME
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Publication number: 20170358687Abstract: Formation of a bottom junction in vertical FET devices may include, for instance, providing an intermediate semiconductor structure comprising a semiconductor substrate, a fin disposed on the semiconductor substrate. The fin has a top surface, spaced-apart vertical sides. A mask is disposed over the top surface of the fin, and at least one is disposed over the vertical sides of the fin. Portions of the substrate are removed to define spaced-apart recesses each extending below a respective one of the spacers. Semiconductor material is grown, such as epitaxially grown, in the recesses.Type: ApplicationFiled: June 13, 2016Publication date: December 14, 2017Applicant: GLOBALFOUNDRIES Inc.Inventors: Hiroaki NIIMI, Kwan-Yong LIM, Steven John BENTLEY, Daniel CHANEMOUGAME
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Patent number: 9842933Abstract: Formation of a bottom junction in vertical FET devices may include, for instance, providing an intermediate semiconductor structure comprising a semiconductor substrate, a fin disposed on the semiconductor substrate. The fin has a top surface, spaced-apart vertical sides. A mask is disposed over the top surface of the fin, and at least one is disposed over the vertical sides of the fin. Portions of the substrate are removed to define spaced-apart recesses each extending below a respective one of the spacers. Semiconductor material is grown, such as epitaxially grown, in the recesses.Type: GrantFiled: June 13, 2016Date of Patent: December 12, 2017Assignee: GLOBALFOUNDRIES Inc.Inventors: Hiroaki Niimi, Kwan-Yong Lim, Steven John Bentley, Daniel Chanemougame
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Publication number: 20170278313Abstract: A device, method, and system may remotely monitor one or more subsystems in a terrestrial vehicle. In one embodiment, a method and system may schedule maintenance and order replacement parts after comparing the reported data with threshold data. In one embodiment, stake-holders, law enforcement entities, government agencies, and national security organizations may access the reported data. In one embodiment, a modular device may monitor vehicle subsystems, vehicle environmental data, a driver's heart beat, a driver's eye activity, a driver's head position, vehicle environmental data, and a driver's ID data.Type: ApplicationFiled: March 22, 2016Publication date: September 28, 2017Inventors: Nermin Maslar, Awais Agha, John Bentley, Bob King, Norman D Dean
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Patent number: 9615266Abstract: In one embodiment, a networking device comprises a first plurality of antenna means, a second plurality of antenna means, and means for controlling the first and second pluralities of antenna means to direct a communication towards a neighbor node of the device.Type: GrantFiled: April 4, 2016Date of Patent: April 4, 2017Assignee: Cisco Technology, Inc.Inventors: Christopher A. Cheadle, Steven Anthony Granzella, John A. Bentley
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Patent number: 9564486Abstract: A method of forming a semiconductor structure includes forming a first isolation region between fins of a first group of fins and between fins of a second group of fins. The first a second group of fins are formed in a bulk semiconductor substrate. A second isolation region is formed between the first group of fins and the second group of fins, the second isolation region extends through a portion of the first isolation region such that the first and second isolation regions are in direct contact and a height above the bulk semiconductor substrate of the second isolation region is greater than a height above the bulk semiconductor substrate of the first isolation region.Type: GrantFiled: August 28, 2015Date of Patent: February 7, 2017Assignees: International Business Machines Corporation, GLOBALFOUNDRIES INC., RENESAS ELECTRONICS CORPORATIONInventors: Murat Kerem Akarvardar, Steven John Bentley, Kangguo Cheng, Bruce B. Doris, Jody Fronheiser, Ajey Poovannummoottil Jacob, Ali Khakifirooz, Toshiharu Nagumo
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Patent number: 9543215Abstract: A method of reducing current leakage in three-dimensional semiconductor devices due to short-channel effects includes providing a starting semiconductor structure, the structure including a semiconductor substrate having a n-type device region and a p-type device region, the p-type device region including an upper layer of p-type semiconductor material, a hard mask layer over both regions, and a mask over the structure for patterning at least one fin in each region. The method further includes creating partial fin(s) in each region from the starting semiconductor structure, creating a conformal liner over the structure, creating a punch-through-stop (PTS) in each region, causing each PTS to diffuse across a top portion of the substrate, and creating full fin(s) in each region from the partial fin(s).Type: GrantFiled: April 20, 2015Date of Patent: January 10, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Kwan-Yong Lim, Steven John Bentley, Chanro Park
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Patent number: 9536793Abstract: Methods for self-aligned gate-first VFETs using gate-spacer recess and the resulting devices are disclosed.Type: GrantFiled: April 22, 2016Date of Patent: January 3, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: John H. Zhang, Kwan-Yong Lim, Steven John Bentley, Chanro Park
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Publication number: 20160307807Abstract: A method of reducing current leakage in three-dimensional semiconductor devices due to short-channel effects includes providing a starting semiconductor structure, the structure including a semiconductor substrate having a n-type device region and a p-type device region, the p-type device region including an upper layer of p-type semiconductor material, a hard mask layer over both regions, and a mask over the structure for patterning at least one fin in each region. The method further includes creating partial fin(s) in each region from the starting semiconductor structure, creating a conformal liner over the structure, creating a punch-through-stop (PTS) in each region, causing each PTS to diffuse across a top portion of the substrate, and creating full fin(s) in each region from the partial fin(s).Type: ApplicationFiled: April 20, 2015Publication date: October 20, 2016Applicant: GLOBALFOUNDRIES INC.Inventors: Kwan-Yong LIM, Steven John BENTLEY, Chanro PARK
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Patent number: 9324790Abstract: A method of forming a semiconductor structure includes forming a first isolation region between fins of a first group of fins and between fins of a second group of fins. The first a second group of fins are formed in a bulk semiconductor substrate. A second isolation region is formed between the first group of fins and the second group of fins, the second isolation region extends through a portion of the first isolation region such that the first and second isolation regions are in direct contact and a height above the bulk semiconductor substrate of the second isolation region is greater than a height above the bulk semiconductor substrate of the first isolation region.Type: GrantFiled: November 19, 2013Date of Patent: April 26, 2016Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, RENESAS ELECTRONICS CORPORATION, GLOBALFOUNDRIES INC.Inventors: Murat Kerem Akarvardar, Steven John Bentley, Kangguo Cheng, Bruce B. Doris, Jody Fronheiser, Ajey Poovannummoottil Jacob, Ali Khakifirooz, Toshiharu Nagumo
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Patent number: D806760Type: GrantFiled: May 23, 2016Date of Patent: January 2, 2018Assignee: Earth & Turf Products, LLCInventor: John A. Bentley
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Patent number: D899724Type: GrantFiled: April 8, 2019Date of Patent: October 20, 2020Inventor: John A. Bentley
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Patent number: D903965Type: GrantFiled: April 20, 2018Date of Patent: December 1, 2020Assignee: Earth & Turf Products, LLCInventor: John A. Bentley
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Patent number: D920387Type: GrantFiled: May 10, 2019Date of Patent: May 25, 2021Assignee: CONESTOGA MANUFACTURING, LLCInventor: John A. Bentley