Patents by Inventor John A. Carelli, Jr.

John A. Carelli, Jr. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7584439
    Abstract: A cell is modeled for use in an integrated circuit design by characterizing the cell based on an input of the cell being driven by a characterization driver having a specified drive strength. A model of the cell is generated which stores an identifier of the characterization driver in association with an identifier of the input. The cell model is then utilized to determine if an actual driver of the input of the cell in the integrated circuit design has a drive strength which is less than that of the characterization driver, and if the actual driver has a drive strength which is less than that of the characterization driver an indicator of this condition is generated. The indicator may, for example, prompt selection of a different driver to replace the actual driver in the integrated circuit design.
    Type: Grant
    Filed: December 7, 2006
    Date of Patent: September 1, 2009
    Assignee: Agere Systems Inc.
    Inventors: John A. Carelli, Jr., Fan Zhou
  • Patent number: 7444275
    Abstract: Techniques are disclosed for modeling a cell of an integrated circuit design. In one aspect of the invention, a full-space polynomial model is fit to cell information comprising measured data points associated with one or more independent variables such as voltage slew, capacitive load, supply voltage or temperature. Error values are generated indicative of error between the measured data points and the full-space polynomial model. The error values are used to partition the modeling space into domains. For at least a given one of the domains, a first polynomial model is generated based on a subset of the measured data points and at least one additional data point determined by interpolation from the measured data points in the subset. Error values are generated indicative of error between the measured data points of the subset and the first polynomial model.
    Type: Grant
    Filed: July 22, 2005
    Date of Patent: October 28, 2008
    Assignee: Agere Systems Inc.
    Inventor: John A. Carelli, Jr.
  • Patent number: 6728940
    Abstract: The present invention provides a method and apparatus for determining when an actual width of a resistor in an integrated circuit varies from a design width for that resistor due to process variations. The method and apparatus may be used to determine an actual amount of the process width variation. This amount may be used to effectively match resistors in an integrated circuit that do not have identical design width. The determination of process width variation in an integrated circuit may be used to match the bias resistor of a integrated current steering digital to analog converter to the converter's output resistors.
    Type: Grant
    Filed: January 18, 2002
    Date of Patent: April 27, 2004
    Assignee: Agere Systems Inc.
    Inventors: John A. Carelli, Jr., Malcolm H. Smith
  • Patent number: 6373266
    Abstract: The present invention provides a method and apparatus for determining when an actual width of a resistor in an integrated circuit varies from a design width for that resistor due to process variations. The method and apparatus may be used to determine an actual amount of the process width variation. This amount may be used to effectively match resistors in an integrated circuit that do not have identical design width. The determination of process width variation in an integrated circuit may be used to match the bias resistor of a integrated current steering digital to analog converter to the converter's output resistors.
    Type: Grant
    Filed: March 31, 2000
    Date of Patent: April 16, 2002
    Assignee: Agere Systems Guardian Corp.
    Inventors: John A. Carelli, Jr., Malcolm H. Smith