Patents by Inventor John A. Cleary
John A. Cleary has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240090721Abstract: A robotic cleaner includes a housing, a suction conduit with an opening, and a leading roller mounted in front of a brush roll. An inter-roller air passageway may be defined between the leading roller and the brush roll wherein the lower portion of the leading roller is exposed to a flow path to the suction conduit and an upper portion of the leading roller is outside of the flow path. Optionally, a combing unit includes a plurality of combing protrusions extending into the leading roller and having leading edges not aligned with a center of the leading roller. Optionally, a sealing strip is located along a rear side of the opening and along a portion of left and right sides of the opening. The underside may define side edge vacuum passageways extending from the sides of the housing partially between the leading roller and the sealing strip towards the opening.Type: ApplicationFiled: November 27, 2023Publication date: March 21, 2024Inventors: Steven Paul CARTER, Adam Udy, Catriona A. Sutter, Christopher Pinches, David S. Clare, Andre David Brown, John Freese, Patrick Cleary, Alexander J. Calvino, Lee Cottrell, Daniel Meyer, Daniel John Innes, David Jalbert, Jason B. Thorne, Peter Hutchinson, Gordon Howes, Wenxiu Gao, David Wu, David W. Poirier, Daniel R. Der Marderosian
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Publication number: 20230221360Abstract: Aspects of this disclosure relate to detecting and recording information associated with electrical overstress (EOS) events, such as electrostatic discharge (ESD) events. For example, in one embodiment, an apparatus includes an electrical overstress protection device, a detection circuit configured to detect an occurrence of the EOS event, and a memory configured to store information indicative of the EOS event.Type: ApplicationFiled: March 22, 2023Publication date: July 13, 2023Inventors: Alan J. O'Donnell, David Aherne, Javier Alejandro Salcedo, David J. Clarke, John A. Cleary, Patrick Martin McGuinness, Albert C. O'Grady
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Patent number: 11644497Abstract: Aspects of this disclosure relate to detecting and recording information associated with electrical overstress (EOS) events, such as electrostatic discharge (ESD) events. For example, in one embodiment, an apparatus includes an electrical overstress protection device, a detection circuit configured to detect an occurrence of the EOS event, and a memory configured to store information indicative of the EOS event.Type: GrantFiled: November 23, 2021Date of Patent: May 9, 2023Assignee: Analog Devices International Unlimited CompanyInventors: Alan J. O'Donnell, David Aherne, Javier Alejandro Salcedo, David J. Clarke, John A. Cleary, Patrick Martin McGuinness, Albert C. O'Grady
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Publication number: 20220082605Abstract: Aspects of this disclosure relate to detecting and recording information associated with electrical overstress (EOS) events, such as electrostatic discharge (ESD) events. For example, in one embodiment, an apparatus includes an electrical overstress protection device, a detection circuit configured to detect an occurrence of the EOS event, and a memory configured to store information indicative of the EOS event.Type: ApplicationFiled: November 23, 2021Publication date: March 17, 2022Inventors: Alan J. O'Donnell, David Aherne, Javier Alejandro Salcedo, David J. Clarke, John A. Cleary, Patrick Martin McGuinness, Albert C. O'Grady
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Patent number: 11203604Abstract: Provided is a process for preparing certain silane precursor compounds, e.g., triiodosilane from trichlorosilane utilizing lithium iodide in powder form and catalyzed by tertiary amines. The process provides triiodosilane in high yields and high purity. Triiodosilane is a precursor compound useful in the atomic layer deposition of silicon onto various microelectronic device structures.Type: GrantFiled: December 6, 2019Date of Patent: December 21, 2021Assignee: Entegris, Inc.Inventors: David Kuiper, Manish Khandelwal, Thomas M. Cameron, Thomas H. Baum, John Cleary
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Patent number: 11193967Abstract: Aspects of this disclosure relate to detecting and recording information associated with electrical overstress (EOS) events, such as electrostatic discharge (ESD) events. For example, in one embodiment, an apparatus includes an electrical overstress protection device, a detection circuit configured to detect an occurrence of the EOS event, and a memory configured to store information indicative of the EOS event.Type: GrantFiled: January 15, 2020Date of Patent: December 7, 2021Assignee: Analog Devices GlobalInventors: Alan J. O'Donnell, David Aherne, Javier Alejandro Salcedo, David J. Clarke, John A. Cleary, Patrick Martin McGuinness, Albert C. O'Grady
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Publication number: 20200380233Abstract: Hardware architectures for ultrasonic front-end receivers used in ultrasonic sensing applications are disclosed. An example ultrasonic receiver may include a plurality of ultrasonic sensor elements. A given ultrasonic sensor element may be configured to detect an ultrasonic signal/wave that has interacted with an object being analyzed, such as a finger, if determining a fingerprint is the target of the ultrasonic sensing. The ultrasonic sensor element is further configured to generate an electrical signal indicative of the ultrasonic signal that has been detected. In contrast to conventional implementations, the electrical signal is integrated in an analog domain, prior to being converted to digital domain for further processing. Various embodiments of the ultrasonic receivers disclosed herein may benefit from one or more of reduced power consumption, reduced die area requirements, and reduced cost due to the use of a more efficient architecture.Type: ApplicationFiled: March 31, 2020Publication date: December 3, 2020Applicant: Analog Devices International Unlimited CompanyInventors: Sudarshan ONKAR, Vinayak AGRAWAL, Ameya PANGARKAR, Gauri MITTAL, Kenneth M. FEEN, John A. CLEARY
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Patent number: 10848107Abstract: Various transimpedance amplifier (TIA) arrangements for ultrasonic front-end receivers used in ultrasonic sensing applications are disclosed. An example TIA includes three common-source gain stages in a feedback loop with a common-gate stage. In some aspects, the TIA may include a level shifter configured to maintain the voltage at the gate of a transistor used to implement the first common-source gain stage of the feedback loop shifted by a certain amount with respect to the voltage at an input port to the TIA. In some aspects, at least portions of the TIA may be biased using bias currents that are configured to be process-, supply voltage-, and/or temperature-dependent. Various embodiments of the TIAs disclosed herein may benefit from one or more of the following advantages: reduced noise, reduced input impedance, reduced temperature coefficient of input impedance, and stability for a wide range of sensor frequencies.Type: GrantFiled: December 6, 2018Date of Patent: November 24, 2020Assignee: ANALOG DEVICES GLOBAL UNLIMITED COMPANYInventors: Sanjay Tumati, Vinayak Agrawal, John A. Cleary
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Patent number: 10700668Abstract: The present disclosure provides a pulse generator which generates a pulse train by mixing pulses of a first clock having a first frequency, with pulses of a second clock having a second frequency. Over a predefined time period, the combination of pulses results in a pulse train having an effective frequency which is between the first and second frequencies. A multiplexer is used to select which of the first and second clocks should be provided to the output. Depending on the desired target frequency, the multiplexer is controlled to mix differing amounts of pulses from the first and second clocks. A multiplexer is controlled by a control signal, which is generated using combinatorial logic using the first clock as an input. The pulse generator may be used, for example, as a clock for a charge pump.Type: GrantFiled: June 15, 2018Date of Patent: June 30, 2020Assignee: Analog Devices Global Unlimited CompanyInventors: David Sayago, Thomas F. Roche, John A. Cleary
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Publication number: 20200181178Abstract: Provided is a process for preparing certain silane precursor compounds, e.g., triiodosilane from trichlorosilane utilizing lithium iodide in powder form and catalyzed by tertiary amines. The process provides triiodosilane in high yields and high purity. Triiodosilane is a precursor compound useful in the atomic layer deposition of silicon onto various microelectronic device structures.Type: ApplicationFiled: December 6, 2019Publication date: June 11, 2020Inventors: David KUIPER, Manish KHANDELWAL, Thomas M. CAMERON, Thomas H. BAUM, John CLEARY
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Publication number: 20200158771Abstract: Aspects of this disclosure relate to detecting and recording information associated with electrical overstress (EOS) events, such as electrostatic discharge (ESD) events. For example, in one embodiment, an apparatus includes an electrical overstress protection device, a detection circuit configured to detect an occurrence of the EOS event, and a memory configured to store information indicative of the EOS event.Type: ApplicationFiled: January 15, 2020Publication date: May 21, 2020Inventors: Alan J. O'Donnell, David Aherne, Javier Alejandro Salcedo, David J. Clarke, John A. Cleary, Patrick Martin McGuinness, Albert C. O'Grady
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Publication number: 20200136565Abstract: Various transimpedance amplifier (TIA) arrangements for ultrasonic front-end receivers used in ultrasonic sensing applications are disclosed. An example TIA includes three common-source gain stages in a feedback loop with a common-gate stage. In some aspects, the TIA may include a level shifter configured to maintain the voltage at the gate of a transistor used to implement the first common-source gain stage of the feedback loop shifted by a certain amount with respect to the voltage at an input port to the TIA. In some aspects, at least portions of the TIA may be biased using bias currents that are configured to be process-, supply voltage-, and/or temperature-dependent. Various embodiments of the TIAs disclosed herein may benefit from one or more of the following advantages: reduced noise, reduced input impedance, reduced temperature coefficient of input impedance, and stability for a wide range of sensor frequencies.Type: ApplicationFiled: December 6, 2018Publication date: April 30, 2020Applicant: Analog Devices Global Unlimited CompanyInventors: Sanjay TUMATI, Vinayak AGRAWAL, John A. CLEARY
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Patent number: 10557881Abstract: Aspects of this disclosure relate to detecting and recording information associated with electrical overstress (EOS) events, such as electrostatic discharge (ESD) events. For example, in one embodiment, an apparatus includes an electrical overstress protection device, a detection circuit configured to detect an occurrence of the EOS event, and a memory configured to store information indicative of the EOS event.Type: GrantFiled: November 1, 2017Date of Patent: February 11, 2020Assignee: Analog Devices GlobalInventors: Alan J. O'Donnell, David Aherne, Javier Alejandro Salcedo, David J. Clarke, John A. Cleary, Patrick Martin McGuinness, Albert C. O'Grady
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Publication number: 20190386643Abstract: The present disclosure provides a pulse generator which generates a pulse train by mixing pulses of a first clock having a first frequency, with pulses of a second clock having a second frequency. Over a predefined time period, the combination of pulses results in a pulse train having an effective frequency which is between the first and second frequencies. A multiplexer is used to select which of the first and second clocks should be provided to the output. Depending on the desired target frequency, the multiplexer is controlled to mix differing amounts of pulses from the first and second clocks. A multiplexer is controlled by a control signal, which is generated using combinatorial logic using the first clock as an input. The pulse generator may be used, for example, as a clock for a charge pump.Type: ApplicationFiled: June 15, 2018Publication date: December 19, 2019Inventors: David SAYAGO, Thomas F. ROCHE, John A. CLEARY
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Publication number: 20190128939Abstract: Aspects of this disclosure relate to detecting and recording information associated with electrical overstress (EOS) events, such as electrostatic discharge (ESD) events. For example, in one embodiment, an apparatus includes an electrical overstress protection device, a detection circuit configured to detect an occurrence of the EOS event, and a memory configured to store information indicative of the EOS event.Type: ApplicationFiled: November 1, 2017Publication date: May 2, 2019Inventors: Alan J. O'Donnell, David Aherne, Javier Alejandro Salcedo, David J. Clarke, John A. Cleary, Patrick Martin McGuinness, Albert C. O'Grady
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Patent number: 9939476Abstract: Embodiments of the present invention may provide a method of measuring an unknown capacitance of a device. The method may comprise the steps of driving a test signal to a circuit system that includes a current divider formed by the device with unknown capacitance and a reference capacitor; mirroring a current developed in the reference capacitor to a second circuit system that includes a measurement impedance; measuring a voltage within the second circuit system; and deriving a capacitance of the unknown capacitance based on the measured voltage with reference to a capacitance of the reference capacitor and the measurement impedance.Type: GrantFiled: September 25, 2015Date of Patent: April 10, 2018Assignee: ANALOG DEVICES GLOBALInventors: Christian Steffen Birk, John A. Cleary, David Sayago Montilla, Elizabeth A. Lillis, Padraig O'Connor, Eoin E. English, Patrick Pratt, Kathleen Embrechts, Wim Rens, Jan Crols
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Patent number: 9871373Abstract: Aspects of this disclosure relate to detecting and recording information associated with electrical overstress (EOS) events, such as electrostatic discharge (ESD) events. For example, in one embodiment, an apparatus includes an electrical overstress protection device, a detection circuit configured to detect an occurrence of the EOS event, and a memory configured to store information indicative of the EOS event.Type: GrantFiled: March 27, 2015Date of Patent: January 16, 2018Assignee: Analog Devices GlobalInventors: Alan J. O'Donnell, David Aherne, Javier Alejandro Salcedo, David J. Clarke, John A. Cleary, Patrick Martin McGuinness, Albert C. O'Grady
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Publication number: 20170366876Abstract: Aspects of the embodiments are directed an analog front end circuit (AFE circuit), the AFE circuit including a beamforming circuit configured to receive as an input a plurality of receiver inputs, the receiver inputs coupled to a sensor element. The beamforming circuit can include a plurality of receiver sub-circuits, each sub-circuit including a digital-to-analog converter, a low noise amplifier, and an I/Q mixer circuit element; an adder circuit element at an output of the I/Q mixer circuit element; and a multiplexer coupled to an output of the adder circuit. The AFE can be part of a current sensing device. The current sensing device can include a two-dimensional array of sensor elements.Type: ApplicationFiled: June 14, 2017Publication date: December 21, 2017Applicant: Analog Devices GlobalInventors: Vinayak Agrawal, Gaurav Gupta, John Cleary, Ken M. Feen
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Publication number: 20170089966Abstract: Embodiments of the present invention may provide a method of measuring an unknown capacitance of a device. The method may comprise the steps of driving a test signal to a circuit system that includes a current divider formed by the device with unknown capacitance and a reference capacitor; mirroring a current developed in the reference capacitor to a second circuit system that includes a measurement impedance; measuring a voltage within the second circuit system; and deriving a capacitance of the unknown capacitance based on the measured voltage with reference to a capacitance of the reference capacitor and the measurement impedance.Type: ApplicationFiled: September 25, 2015Publication date: March 30, 2017Applicant: ANALOG DEVICES GLOBALInventors: Christian Steffen Birk, John A. Cleary, David Sayago Montilla, Elizabeth A. Lillis, Padraig O'Connor, Eoin E. English, Patrick Pratt, Kathleen Embrechts, Wim Rens, Jan Crols
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Patent number: 9525407Abstract: A power supply monitoring circuit for monitoring a voltage at a power supply node compared to a reference node, the power supply monitoring circuit comprising a first field effect transistor and first and second voltage dropping components arranged in current flow communication between the power supply node and the reference node and each having first and second nodes, and wherein a first node of the first voltage dropping component is connected to one of the first and second nodes of the field effect transistor, and a gate of the field effect transistor is connected to the second node of the first voltage dropping component, and an output signal is taken from a connection made with the first field effect transistor.Type: GrantFiled: March 11, 2014Date of Patent: December 20, 2016Assignee: Analog Devices GlobalInventors: Santiago Iriarte, John A. Cleary