Abstract: A method and apparatus for reducing the power consumption of an integrated circuit when the core logic of the integrated circuit is in the quiescent or idle state. The method and apparatus includes a phase locked loop (PLL) circuit for generating an internal clock, wherein the frequency of the internal clock is at a predetermined multiple of the frequency of the global clock signal. When the integrated circuit is quiescent, the present invention provides circuitry which permits the internal clock to be slowed to a lower frequency or the internal clock to be frozen to reduce power consumption.