Patents by Inventor John A. DeNisco

John A. DeNisco has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8755393
    Abstract: In certain embodiments, facilitating communication of routing information includes receiving, at a shim, incoming messages communicating routing information from a first protocol point of one or more protocol points operating according to a routing protocol. The shim belongs to an internal region separate from an external region, and a transport layer is disposed between the shim and the protocol points. The incoming messages are processed and sent to siblings that belong to the internal region. Each sibling implements a state machine for the routing protocol. Outgoing messages are received from a first sibling. The outgoing messages are processed and sent to a second protocol point of the one or more protocol points.
    Type: Grant
    Filed: April 2, 2010
    Date of Patent: June 17, 2014
    Assignee: Cisco Technology, Inc.
    Inventors: Richard A. Payne, Andrei Agapi, Robert M. Broberg, Ralph H. Castain, John A. DeNisco
  • Patent number: 8352776
    Abstract: In certain embodiments, replicating data elements includes calculating a key value for a data element. The key value is calculated from at least a part of content of the first data element. K computing elements are automatically selected from X computing element nodes according to the key value and a mapping schema. K is a greater than 2 and less than X. The computing element nodes each include computer-readable memory embodied within one or more routers. K replications of the data element are automatically written to the computer-readable memory of the K computing element nodes.
    Type: Grant
    Filed: April 2, 2010
    Date of Patent: January 8, 2013
    Assignee: Cisco Technology, Inc.
    Inventors: Andrei Agapi, Richard A. Payne, Robert M. Broberg, John A. DeNisco
  • Publication number: 20110246814
    Abstract: In certain embodiments, replicating data elements includes calculating a key value for a data element. The key value is calculated from at least a part of content of the first data element. K computing elements are automatically selected from X computing element nodes according to the key value and a mapping schema. K is a greater than 2 and less than X. The computing element nodes each include computer-readable memory embodied within one or more routers. K replications of the data element are automatically written to the computer-readable memory of the K computing element nodes.
    Type: Application
    Filed: April 2, 2010
    Publication date: October 6, 2011
    Applicant: Cisco Technology, Inc.
    Inventors: Andrei Agapi, Richard A. Payne, Robert M. Broberg, John A. DeNisco
  • Publication number: 20110243150
    Abstract: In certain embodiments, facilitating communication of routing information includes receiving, at a shim, incoming messages communicating routing information from a first protocol point of one or more protocol points operating according to a routing protocol. The shim belongs to an internal region separate from an external region, and a transport layer is disposed between the shim and the protocol points. The incoming messages are processed and sent to siblings that belong to the internal region. Each sibling implements a state machine for the routing protocol. Outgoing messages are received from a first sibling. The outgoing messages are processed and sent to a second protocol point of the one or more protocol points.
    Type: Application
    Filed: April 2, 2010
    Publication date: October 6, 2011
    Applicant: Cisco Technology, Inc.
    Inventors: Richard A. Payne, Andrei Agapi, Robert M. Broberg, Ralph H. Castain, John A. DeNisco
  • Patent number: 6470013
    Abstract: A technique for configuring address information automatically for intelligent port cards such as in a cell multiplexer, router, or other internetwork device. A maintenance or control processor is included in the device together with a number of, for example, line and trunk units. The line and trunk units are loaded, monitored, and controlled by the controller via a backplane network. The backplane network must be assigned a subnet address which does not conflict with the management network interface also on the controller. In order to accomplish this, a LINK_LOOP broadcast packet is periodically sent over the backplane network containing the IP subnet address of the current master system controller. Line and trunk cards in a configuration state therefore wait to hear such a datagram configure their own IP addresses and to acquire the system controller IP address based on the message contents and then are able to initiate IOS IPC protocol over the backplane network as required.
    Type: Grant
    Filed: October 13, 1998
    Date of Patent: October 22, 2002
    Assignee: Cisco Technology, Inc.
    Inventors: David R. Barach, John A. DeNisco, Robert J. Goguen
  • Patent number: 5406504
    Abstract: An arrangement for a multiprocessor RISC system enables each CPU of the system to test the control logic of its cache by indirectly examining states of the caches and comparing those states to predetermined valid cache states of the system. The arrangement includes a plurality of processes configured to acquire information from selected block entries of the caches. The information is then compared with an array of predetermined valid cache states contained in a state table to detect invalid cache states. A cache examining protocol defines the operational procedures followed by the processes when acquiring and examining the information.
    Type: Grant
    Filed: June 30, 1993
    Date of Patent: April 11, 1995
    Assignee: Digital Equipment
    Inventors: John A. Denisco, Arthur J. Beaverson