Patents by Inventor John A. Dickerson
John A. Dickerson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240152810Abstract: A method for monitoring performance of a ML system includes receiving a data stream via a processor and generating a first plurality of metrics based on the data stream. The processor also generates input data based on the data stream, and sends the input data to a machine learning (ML) model for generation of intermediate output and model output based on the input data. The processor also generates a second plurality of metrics based on the intermediate output, and a third plurality of metrics based on the model output. An alert is generated based on at least one of the first plurality of metrics, the second plurality of metrics, or the third plurality of metrics, and a signal representing the alert is sent for display to a user via an interface.Type: ApplicationFiled: January 16, 2024Publication date: May 9, 2024Applicant: Arthur AI, Inc.Inventors: Adam WENCHEL, John DICKERSON, Priscilla ALEXANDER, Elizabeth O'SULLIVAN, Keegan HINES
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Patent number: 11922280Abstract: A method for monitoring performance of a ML system includes receiving a data stream via a processor and generating a first plurality of metrics based on the data stream. The processor also generates input data based on the data stream, and sends the input data to a machine learning (ML) model for generation of intermediate output and model output based on the input data. The processor also generates a second plurality of metrics based on the intermediate output, and a third plurality of metrics based on the model output. An alert is generated based on at least one of the first plurality of metrics, the second plurality of metrics, or the third plurality of metrics, and a signal representing the alert is sent for display to a user via an interface.Type: GrantFiled: December 9, 2020Date of Patent: March 5, 2024Assignee: Arthur AI, Inc.Inventors: Adam Wenchel, John Dickerson, Priscilla Alexander, Elizabeth O'Sullivan, Keegan Hines
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PARTICLE MANIPULATION SYSTEM WITH CYTOMETRIC CAPABILITY AND FEEDBACK LOOP AND VARIABLE GAIN DETECTOR
Publication number: 20240067920Abstract: A MEMS-based particle manipulation system which uses a particle manipulation stage and a plurality of laser interrogation regions. The laser interrogation regions may be used to assess the effectiveness or accuracy of the particle manipulation stage. In one exemplary embodiment, the particle manipulation stage is a microfabricated, flap-type fluid valve, which sorts a target particle from non-target particles in a fluid stream. The laser interrogation stages are disposed in the microfabricated fluid channels at the input and output of the flap-type sorting valve. The laser interrogation regions may be used to assess the effectiveness or accuracy of the sorting, and to control or adjust sort parameters during the sorting process. One or more feedback loops may be used to improve the particle manipulation process, based on data acquired during the first interrogation and/or during a downstream confirmation. Artificial intelligence techniques may be used to good effect.Type: ApplicationFiled: August 28, 2023Publication date: February 29, 2024Applicant: Owl biomedical, Inc.Inventors: Paul Hing, Nathaniel BAIR, Daryl GRUMMITT, John Harley, Mark NAIVAR, Matthew DICKERSON -
Patent number: 11403538Abstract: In an embodiment, the systems and methods discussed herein are related to generating, via a processor, a Markov Decision Process (MDP), the MDP including a state space, an action space, a transition function, a reward function, and a discount factor. A reinforcement learning (RL) model is applied, via the processor, to the MDP to generate a RL agent. An input data associated with a first user is received at the RL agent. At least one counterfactual explanation (CFE) is generated via the processor and by the RL agent and based on the input data. A representation of the at least one CFE and at least one recommended remedial action is caused to transmit, via the processor, to at least one of a compute device of the first user or a compute device of a second user different from and associated with the first user.Type: GrantFiled: November 5, 2021Date of Patent: August 2, 2022Assignee: Arthur AI, Inc.Inventors: Sahil Verma, John Dickerson, Keegan Hines
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Publication number: 20210174258Abstract: A method for monitoring performance of a ML system includes receiving a data stream via a processor and generating a first plurality of metrics based on the data stream. The processor also generates input data based on the data stream, and sends the input data to a machine learning (ML) model for generation of intermediate output and model output based on the input data. The processor also generates a second plurality of metrics based on the intermediate output, and a third plurality of metrics based on the model output. An alert is generated based on at least one of the first plurality of metrics, the second plurality of metrics, or the third plurality of metrics, and a signal representing the alert is sent for display to a user via an interface.Type: ApplicationFiled: December 9, 2020Publication date: June 10, 2021Inventors: Adam WENCHEL, John DICKERSON, Priscilla ALEXANDER, Elizabeth O'SULLIVAN, Keegan HINES
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Patent number: 7518355Abstract: A system and method for voltage sensing at active power gated cores of a multi core CPU wherein a Controlled Collapse Chip Carrier bump in a gating region for an associated core is isolatable from an ungated power region by a power gate to allow voltage sensing at a designated location with substantially no current passing there through.Type: GrantFiled: March 30, 2007Date of Patent: April 14, 2009Assignee: Intel CorporationInventors: Michael Grassi, Alex Levin, John Dickerson
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Publication number: 20080238407Abstract: A system and method for voltage sensing at active power gated cores of a multi core CPU wherein a Controlled Collapse Chip Carrier bump in a gating region for an associated core is isolatable from an ungated power region by a power gate to allow voltage sensing at a designated location with substantially no current passing there through.Type: ApplicationFiled: March 30, 2007Publication date: October 2, 2008Applicant: INTEL CORPORATIONInventors: Michael Grassi, Alex Levin, John Dickerson
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Publication number: 20060203970Abstract: The monitor is for monitoring the status of a first client telephone, and for sending this status information via a central server to an authorized second client telephone. The central server stores a database of registered client telephones and corresponding client telephones that the client may monitor. A user of a registered client telephone monitors in real time the telephone status of registered friends, family, or co-workers that have agreed to be monitored by the user.Type: ApplicationFiled: June 1, 2006Publication date: September 14, 2006Inventors: James Jorasch, Jay Walker, Magdalena Fincham, John Dickerson, Marc Kessman, Geoffrey Gelman, Stephen Tulley, Dean Alderucci
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Publication number: 20060203969Abstract: The monitor is for monitoring the status of a first client telephone, and for sending this status information via a central server to an authorized second client telephone. The central server stores a database of registered client telephones and corresponding client telephones that the client may monitor. A user of a registered client telephone monitors in real time the telephone status of registered friends, family, or co-workers that have agreed to be monitored by the user.Type: ApplicationFiled: June 1, 2006Publication date: September 14, 2006Inventors: James Jorasch, Jay Walker, Magdalena Fincham, John Dickerson, Marc Kessman, Geoffrey Gelman, Stephen Tulley, Dean Alderucci
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Publication number: 20060203968Abstract: The monitor is for monitoring the status of a first client telephone, and for sending this status information via a central server to an authorized second client telephone. The central server stores a database of registered client telephones and corresponding client telephones that the client may monitor. A user of a registered client telephone monitors in real time the telephone status of registered friends, family, or co-workers that have agreed to be monitored by the user.Type: ApplicationFiled: June 1, 2006Publication date: September 14, 2006Inventors: James Jorasch, Jay Walker, Magdalena Fincham, John Dickerson, Marc Kessman, Geoffrey Gelman, Stephen Tulley, Dean Alderucci
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Publication number: 20060140350Abstract: The monitor is for monitoring the status of a first client telephone, and for sending this status information via a central server to an authorized second client telephone. The central server stores a database of registered client telephones and corresponding client telephones that the client may monitor. A user of a registered client telephone monitors in real time the telephone status of registered friends, family, or co-workers that have agreed to be monitored by the user.Type: ApplicationFiled: December 23, 2005Publication date: June 29, 2006Inventors: James Jorasch, Jay Walker, Magdalena Fincham, John Dickerson, Marc Kessman, Geoffrey Gelman, Stephen Tulley, Dean Alderucci
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Publication number: 20060133581Abstract: The monitor is for monitoring the status of a first client telephone, and for sending this status information via a central server to an authorized second client telephone. The central server stores a database of registered client telephones and corresponding client telephones that the client may monitor. A user of a registered client telephone monitors in real time the telephone status of registered friends, family, or co-workers that have agreed to be monitored by the user.Type: ApplicationFiled: January 24, 2006Publication date: June 22, 2006Inventors: James Jorasch, Jay Walker, Magdalena Fincham, John Dickerson, Marc Kessman, Geoffrey Gelman, Stephen Tulley, Dean Alderucci
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Publication number: 20060129456Abstract: According to some embodiments, systems, methods, and/or articles of manufacture are associated with identifying a product associated with a first rebate, the first rebate being redeemable by mailing a predetermined document associated with the first rebate to a first entity associated with the product, determining whether a second rebate is associated with the product, wherein the second rebate is not identified by the predetermined document associated with the first rebate, offering, in the case that the second rebate is determined to be associated with the product, the second rebate to a consumer in exchange for the first rebate, and issuing the second rebate to the consumer in exchange for the first rebate.Type: ApplicationFiled: December 22, 2005Publication date: June 15, 2006Inventors: Jay Walker, James Jorasch, Daniel Tedesco, John Packes, Keith Bemer, John Dickerson
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Publication number: 20060004032Abstract: The preferred embodiments generally relate to methods and compositions that affect the GTP-binding activity of members of the Rho family GTPases, preferably Rac (Rac1, Rac2 and/or Rac3), such compositions include compounds that modulate the GTP/GDP exchange activity, along with uses for the compounds including screening for compounds which recognize Rac GTPase, and methods of treating pathological conditions associated or related to a Rho family GTPase, including Rac. The preferred embodiments also relate to methods of using such compounds, or derivatives thereof, e.g., in therapeutics, diagnostics, and as research tools.Type: ApplicationFiled: November 19, 2004Publication date: January 5, 2006Inventors: Yi Zheng, Jie Zheng, Yuan Gao, John Dickerson, Wieslaw Mazur
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Publication number: 20050219867Abstract: A system may include a voltage regulator converter, the voltage regulator converter comprising N (N>1) phases, and a voltage regulator controller coupled to the voltage regulator converter and to control the voltage regulator converter to generate a first current within a first one of the N phases and to generate a second current within a second one of the N phases, wherein the first current is different from the second current.Type: ApplicationFiled: March 30, 2004Publication date: October 6, 2005Inventors: Mai Loc, John Dickerson, Peter Li
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Publication number: 20040117673Abstract: A method and apparatus are provided to power a processor coupled to a package. This may include determining a type of processor coupled to the package and adjusting characteristics of a load line to power the processor based on the determined type of processor.Type: ApplicationFiled: December 17, 2002Publication date: June 17, 2004Inventors: Tawfik Arabi, Michael Stapleton, John Dickerson, Hung-Piao (Matthew) Ma, Michael T. Zhang
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Patent number: 6574577Abstract: A system includes a processor, a voltage regulator and a circuit. The processor uses a first supply voltage to furnish a first indication of a second supply voltage to be received by the processor. The voltage regulator furnishes the second supply voltage in response to both the first indication and a second indication that the first supply voltage is valid. The circuit provides the second indication and regulates a timing of the second indication to prevent the voltage regulator from furnishing the second supply voltage until a predefined interval of time has elapsed after the first supply voltage becomes valid.Type: GrantFiled: December 13, 2000Date of Patent: June 3, 2003Assignee: Intel CorporationInventors: Michael A. Stapleton, Bernard W. Boland, Jeffery J. Olsen, John A. Dickerson
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Patent number: 6462438Abstract: A method includes converting a first voltage into a second voltage. The second voltage is routed to a power supply line when the second voltage exceeds a first predefined threshold, and the second voltage is isolated from the power supply line when the first voltage decreases below a second predefined voltage.Type: GrantFiled: September 27, 2000Date of Patent: October 8, 2002Assignee: Intel CorporationInventors: Michael A. Stapleton, Bernard W. Boland, Jeffery J. Olsen, John A. Dickerson
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Publication number: 20020072871Abstract: A system includes a processor, a voltage regulator and a circuit. The processor uses a first supply voltage to furnish a first indication of a second supply voltage to be received by the processor. The voltage regulator furnishes the second supply voltage in response to both the first indication and a second indication that the first supply voltage is valid. The circuit provides the second indication and regulates a timing of the second indication to prevent the voltage regulator from furnishing the second supply voltage until a predefined interval of time has elapsed after the first supply voltage becomes valid.Type: ApplicationFiled: December 13, 2000Publication date: June 13, 2002Inventors: Michael A. Stapleton, Bernard W. Boland, Jeffery J. Olsen, John A. Dickerson
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Patent number: 6316924Abstract: A system includes a first power supply line that is associated with a first voltage level and a second power supply line that is associated with a second voltage level. A power supply is coupled to the first and second power lines to establish a first voltage of the first power supply line near the first voltage level and a second voltage of the second power supply line near the second voltage level. The power supply has a response during a time period after the activation or deactivation of the power supply in which the power supply does not maintain a difference between the first and second voltages within a predefined range. The system includes a circuit that is coupled to the first and second power supply lines to maintain the difference between the first and second voltages within the predefined range during the time period.Type: GrantFiled: June 29, 2000Date of Patent: November 13, 2001Assignee: Intel CorporationInventors: Michael A. Stapleton, Bernard W. Boland, Jeffery J. Olsen, John A. Dickerson