Abstract: A printed circuit board (PCB)-mounted contactor including a PCB with planar surface, source and load terminals fixed to the PCB, and a contact. The contact is supported by the PCB and is movable between open and closed positions. Movement of the contact is parallel to the planar surface. Electrical assemblies having PCB-mounted contactors and methods of controlling current flow in electrical systems with PCB-mounted contactors are also described.

Abstract: A power distribution assembly according to an example of the present disclosure includes, among other things, a housing at least partially receiving a plurality of hardware modules coupled to a backplane, the plurality of hardware modules including at least one output module and a communications module that communicates information between the plurality of hardware modules and a second power distribution assembly. At least one hardware module of the plurality of hardware modules includes a field programmable gate array that commands the at least one output module to selectively power at least one aircraft system. A method of operation of a power distribution system is also disclosed.

Abstract: A system for testing a transient voltage suppressor (TVS) configured to be coupled between a bus and a first ground or line to discharge a voltage surge on the bus to the first ground or line includes a pulse source configured to generate an electrical pulse. The system further includes a transformer having a first side coupled to the pulse source and a second side configured to be coupled to the TVS and configured to transfer the electrical pulse to the TVS and to transfer an at least partial reflection of the electrical pulse from the TVS to the first side. The system also includes a test point coupled to the first side of the transformer and configured to receive the at least partial reflection of the electrical pulse.

Abstract: Embodiments are directed to a transient protection circuit configured for use in a SSPC having a plurality of power channels. The transient protection circuit includes a shared transient voltage suppressor, and a shared protection line communicatively coupled to the shared transient voltage suppressor. The shared protection line is configured to be communicatively coupled to and shared by the plurality of power channels. When the shared protection line is communicatively coupled to and shared by the plurality of power channels, energy above a threshold on any one of the plurality of power channels is dissipated through the shared protection line and the shared transient voltage suppressor.

Abstract: A system balances current flowing through a solid-state power controller system including at least two output channels connected in parallel. The system delivers a first current to a load via a first output channel to a load, and delivers a second current to the load via a second output channel connected in parallel with the first output channel. The system further determines a first strength of the first current and a second strength of the second current, and adjusts at least one of a first resistance of the first output channel and a second resistance of the second output channel such that the first current strength is substantially equal to the second current strength.

Abstract: A system for mitigating a solid state power controller (SSPC) open or closed state change caused by single event latchup (SEL) includes an ON circuit, an OFF circuit operatively connected in parallel to the ON circuit, a holding capacitor operatively connected in parallel with the ON circuit and the OFF circuit, and a power switching device operatively connected to the holding capacitor and the ON circuit. The system is configured to maintain, during and after the SEL, a drive state voltage to the power switching device that is stored in the holding capacitor prior to the SEL.

Abstract: A transistor module assembly includes a longitudinally extending load bus bar, a longitudinally extending feed bus bar parallel to the load bus bar, and at least one transistor package operatively connected to the load and feed bus bars. The transistor package includes a drain surface and a source lead. The drain surface is operatively connected to the feed bus bar for receiving current therefrom. The source lead is operatively connected to the load bus bar for dissipating current from the transistor package to the load bus bar.

Abstract: In accordance with another aspect, a power switch assembly includes a transistor package including a die case, a source bus tab extending from a first side of the die case, a drain bus tab extending from a second side of the die case, a first power bus rail operatively connected to the source bus tab of the transistor package and a second power bus rail operatively connected to the drain bus tab of the transistor package.

Abstract: Embodiments include a technique for eliminating secondary fuses in high power solid state power controllers, the technique includes controlling gate power provided to a field effect transistor array, and detecting a failure mode. The technique also includes disabling the gate power based at least in part on detecting the failure mode, and restoring the gate power responsive to resolving the failure mode.

Abstract: A load balancing circuit comprising a first power source, a first field effect transistor (FET) device having a drain terminal connected to the first power source and a source terminal connected to a first node, a first resistor connected to the first node and a second node, a load connected to the second node, a second FET device having a drain terminal connected to the first node and a source terminal connected to the second node, a third FET device having a collector terminal connected to a gate terminal of the first FET device and an emitter terminal connected to the second node, and a second resistor connected to a base terminal of the third FET device and the first node.

Abstract: Embodiments are directed to a lightning protection circuit configured for use in a solid state power controller (SSPC) having at least one feed line and a plurality of load lines. The lightning protection circuit includes a shared transient voltage suppressor and a transient isolator communicatively coupled to the shared transient voltage suppressor. The transient isolator is configured to be communicatively coupled to the at least one feed line and the plurality of load lines. When the transient isolator is communicatively coupled to and shared by the at least one feed line and the plurality of load lines, energy above a threshold on any one of the at least one feed line and the plurality of load lines is dissipated through the shared transient voltage suppressor. A single built-in-test (BIT) circuit is provided to detect dormant failures of the shared transient voltage suppressor.

Abstract: A load balancing circuit comprising a first power source, a first field effect transistor (FET) device having a drain terminal connected to the first power source and a source terminal connected to a first node, a first resistor connected to the first node and a second node, a load connected to the second node, a second FET device having a drain terminal connected to the first node and a source terminal connected to the second node, a third FET device having a collector terminal connected to a gate terminal of the first FET device and an emitter terminal connected to the second node, and a second resistor connected to a base terminal of the third FET device and the first node.

Abstract: A solid-state power controller (SSPC) includes two or more SSPC channels for connecting a load to a feed bus. The SSPC channels include a disconnect switch and an enable switch having a terminal connected to a gate of the disconnect switch. A voltage clamping diode of the SSPC channel is connected to the gate of the enable switch, and is arranged to close the enable switch when a transient voltage applied to the SSPC channel when the transient voltage exceeds the breakdown voltage of the voltage clamping diode.

Abstract: A system for differential current monitoring includes a control module and a plurality of nodes operatively connected to the control module. Each node is configured to monitor current from a bus to a respective load. The control module and nodes are configured to monitor current at each of the nodes, issue a pulse for each node, wherein the pulse has a duration that is proportional to current at the node, concatenate all of the pulses for the nodes to determine the total current drawn from the bus at the nodes, compare the total current drawn from the bus at the nodes to current input to the bus, and signal a fault condition if the total current drawn from the bus is not within a predetermined range of the current input to the bus.

Abstract: A system for mitigating a solid state power controller (SSPC) open or closed state change caused by single event latchup (SEL) includes an ON circuit, an OFF circuit operatively connected in parallel to the ON circuit, a holding capacitor operatively connected in parallel with the ON circuit and the OFF circuit, and a power switching device operatively connected to the holding capacitor and the ON circuit. The system is configured to maintain, during and after the SEL, a drive state voltage to the power switching device that is stored in the holding capacitor prior to the SEL.

Abstract: A system and method to manage a single event latched (SEL) condition, the method including operations to monitor, for a predetermined condition associated with single event latched (SEL) states, a reset signal output from a watchdog device to a microprocessor, wherein the reset signal is responsive to a malfunction condition associated with the microprocessor. The method further includes operations to control provision of power to the microprocessor in response to detection of the predetermined condition.

Abstract: A method for fabricating a circuit board apparatus includes providing a circuit board that has a socket with at least one plated through-hole and providing a connector that has a housing with first and second connector interfaces that have, respectively, at least first and second connector contacts. The first connector interface opens into an interior of the housing such that there is a vapor path through the first connector interface and interior of the housing to the second connector contact at the second connector interface. The first connector contact is inserted through the resilient seal and into the plated through-hole such that the resilient seal intimately seals around the first connector contact to provide a barrier at the first connector interface into the vapor path.

Abstract: A circuit comprises an alternating current (AC) feed line, a solid state power controller portion connected to the AC feed line, a load connected to the solid state power controller portion, a positive clamp rail, a negative clamp rail, a ground, a first diode connected to the AC feed line and the positive clamp rail, a second diode connected to the AC feed line and the negative clamp rail, a third diode connected to the load and the positive clamp rail, a fourth diode connected to the load and the negative clamp rail, a fifth diode connected to the positive clamp rail and the ground, a sixth diode connected to the negative clamp rail and the ground, and a capacitor connected to the positive clamp rail and the negative clamp rail.

Abstract: A multi-channel power controller includes a main controller communicatively coupled to a plurality of standard power control circuit boards. Each of the standard power controller circuit boards includes a nexus having a plurality of virtual channels and a plurality of solid state power controllers. Each of the solid state power controllers is controlled by one of the virtual channels. A plurality of physical control channels operable to control power to at least one load. Each physical control channel of the plurality of physical control channels is controlled by a corresponding solid state power controller of the plurality of solid state power controllers. At least one of the virtual channels controls more than one of the physical control channels in the plurality of physical control channels.

Abstract: A system and method to manage a single event latched (SEL) condition, the method including operations to monitor, for a predetermined condition associated with single event latched (SEL) states, a reset signal output from a watchdog device to a microprocessor, wherein the reset signal is responsive to a malfunction condition associated with the microprocessor. The method further includes operations to control provision of power to the microprocessor in response to detection of the predetermined condition.