Patents by Inventor John A. Dungan

John A. Dungan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090261571
    Abstract: This disclosure concerns a method and apparatus that prints travel documents. The method may include retrieving a travel document template, wherein the travel document template is in a format dictated by an industry standard, receiving travel document data for an individual's travel, integrating the individual's travel document data with the travel document template to produce a digital image of one or more travel documents that includes the integrating travel document data and the travel document template, and outputting the one or more travel document.
    Type: Application
    Filed: April 18, 2008
    Publication date: October 22, 2009
    Applicant: ARINC INCORPORATED
    Inventors: John A. Dungan, William Henry Herleth
  • Publication number: 20070228562
    Abstract: Formation of a plurality of conductive connectors of an integrated circuit package is described. The conductive connectors made with a conductive elastomer material and formed using an interposer that includes a plurality of the conductive connectors linked together.
    Type: Application
    Filed: June 11, 2007
    Publication date: October 4, 2007
    Inventors: David Boggs, John Dungan, Frank Sanders, Daryl Sato, Dan Willis
  • Publication number: 20070082512
    Abstract: A generally planar interposer having a plurality of interposer contact pads to contact a plurality of first contacts of a first electronic device on one side of the interposer, and a plurality of electrical connections between the interposer contact pads and a plurality of pressure contacts on the other side of the interposer. Each of the pressure contacts having a directionally deformable contact surface to removably contact a plurality of second contacts of a second electronic device on the other side of the interposer. Also methods of forming the interposer.
    Type: Application
    Filed: December 8, 2006
    Publication date: April 12, 2007
    Inventors: David Boggs, John Dungan, Frank Sanders, Daryl Sato, Dan Willis
  • Patent number: 7147141
    Abstract: A method for providing an improved solder joint for a via-in-pad ball grid array package. One or more bonding pads are formed upon a substrate. One or more vias are formed through the substrate within the bonding pad. The vias are plugged with a via plug material. The via plug material is then preconditioned such that an amount of volatiles within the via plug material is reduced.
    Type: Grant
    Filed: November 13, 2002
    Date of Patent: December 12, 2006
    Assignee: Intel Corporation
    Inventors: Daryl Sato, Gary Paek, John Dungan, David W. Boggs
  • Patent number: 7061116
    Abstract: An arrangement of pads with selective via in pad for mounting a semiconductor package on a substrate. In order to strengthen the soldered bonds, standard pads, which have a stronger bond, are used in locations of greatest stress and deflection. Vias in pad (VIP) are used at all other locations to improve routing advantages due to their smaller surface area.
    Type: Grant
    Filed: September 26, 2001
    Date of Patent: June 13, 2006
    Assignee: Intel Corporation
    Inventors: Carolyn McCormick, Rebecca Jessep, John Dungan, David W. Boggs, Daryl Sato
  • Publication number: 20050242434
    Abstract: Formation of a plurality of conductive connectors of an integrated circuit package is described. The conductive connectors made with a conductive elastomer material and formed using an interposer that includes a plurality of the conductive connectors linked together.
    Type: Application
    Filed: April 30, 2004
    Publication date: November 3, 2005
    Inventors: David Boggs, John Dungan, Frank Sanders, Daryl Sato, Dan Willis
  • Publication number: 20050142900
    Abstract: A generally planar interposer having a plurality of interposer contact pads to contact a plurality of first contacts of a first electronic device on one side of the interposer, and a plurality of electrical connections between the interposer contact pads and a plurality of pressure contacts on the other side of the interposer. Each of the pressure contacts having a directionally deformable contact surface to removably contact a plurality of second contacts of a second electronic device on the other side of the interposer. Also methods of forming the interposer.
    Type: Application
    Filed: December 31, 2003
    Publication date: June 30, 2005
    Inventors: David Boggs, John Dungan, Frank Sanders, Daryl Sato, Dan Willis
  • Publication number: 20050063166
    Abstract: A device includes a plane metallization layer, and a plane plated through hole attached to the plane metallization layer and terminating at the at a major exterior surface with a plurality of component mounting pads. The plated through hole is attached to the plane metallization layer. The plane plated through hole is electrically isolated from the plurality of component mounting pads at the exterior surface. A method for testing the device includes contacting the signal carrying through hole, and contacting the plane through hole, and checking for current flow between the signal carrying through hole and the plane through hole. If current flows between the signal carrying through hole and the plane through hole the device fails. If no current flows between the signal carrying through hole and the plane through hole the device passes.
    Type: Application
    Filed: September 23, 2003
    Publication date: March 24, 2005
    Inventors: David Boggs, John Dungan, Daryl Sato
  • Publication number: 20040129453
    Abstract: Embodiments of substrate in accordance with the present invention provide interconnect cavities for direct interconnection between SMT components and internal conductive inner layers, as well as surface outer layers. Interconnect cavities eliminate the need for through hole vias and require less substrate surface area and internal volume. Each interconnect cavity comprises a cavity extending from the substrate surface to an adjacent internal conductive inner layer directly beneath the cavity. The cavity extends through a conductive outer layer on the substrate surface. The cavity has a conductive liner interconnected with the outer layer and the inner layer forming a cup-shaped conductive depression interconnecting the outer layer with the inner layer.
    Type: Application
    Filed: January 7, 2003
    Publication date: July 8, 2004
    Inventors: David W. Boggs, Daryl Sato, John Dungan
  • Publication number: 20040089700
    Abstract: A method for providing an improved solder joint for a via-in-pad ball grid array package. One or more bonding pads are formed upon a substrate. One or more vias are formed through the substrate within the bonding pad. The vias are plugged with a via plug material. The via plug material is then preconditioned such that an amount of volatiles within the via plug material is reduced.
    Type: Application
    Filed: November 13, 2002
    Publication date: May 13, 2004
    Inventors: Daryl Sato, Gary Paek, John Dungan, David W. Boggs
  • Publication number: 20030057974
    Abstract: An arrangement of vias for mounting a semiconductor package on a substrate. In order to strengthen the soldered bonds, standard vias, which have a stronger bond, are used in locations of greatest stress and deflection. Vias in pad (VIP) are used at all other locations to improve routing advantages due to their smaller surface area.
    Type: Application
    Filed: September 26, 2001
    Publication date: March 27, 2003
    Inventors: Carolyn McCormick, Rebecca Jessep, John Dungan, David W. Boggs, Daryl Sato