Patents by Inventor John A. Fifield

John A. Fifield has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Voltage detection circuit and circuit for generating a trigger flag signal
    Patent number: 7466171
    Abstract: An integrated circuit that includes at least one tunneling device voltage detection circuit for generating a trigger flag signal. The tunneling device voltage detection circuit includes first and second voltage dividers receiving a supply voltage and having corresponding respective first and second internal node output voltages. The first and second voltage dividers are configured so the first output voltage is linear relative to the supply voltage and so that the second output voltage is nonlinear relative to the supply voltage. As the supply voltage ramps up, the profiles of the first and second output voltage cross at a particular voltage. An operational amplifier circuit senses when the first and second output voltages become equal and, in response thereto, outputs a trigger signal that indicates that the supply voltage has reached a certain level.
    Type: Grant
    Filed: January 15, 2007
    Date of Patent: December 16, 2008
    Assignee: International Business Machines Corporation
    Inventors: Wagdi W. Abadeer, Jeffrey S. Brown, Albert M. Chu, John A. Fifield
  • Programmable Heavy-Ion Sensing Device for Accelerated Dram Soft Error Detection
    Publication number: 20080273393
    Abstract: Aspects of the invention relate to a programmable heavy-ion sensing device for accelerated DRAM soft error detection. Design of a DRAM-based alpha particle sensing apparatus is preferred to be used as an accelerated on-chip SER test vehicle. The sensing apparatus is provided with programmable sensing margin, refresh rate, and supply voltage to achieve various degree of SER sensitivity. In addition, a dual-mode DRAM array is proposed so that at least a portion of the array can be used to monitor high-energy particle activities during soft-error detection (SED) mode.
    Type: Application
    Filed: March 21, 2007
    Publication date: November 6, 2008
    Inventors: Howard H. Chen, John A. Fifield, Louis L. Hsu, Henry H. K. Tang
  • Programmable Heavy-Ion Sensing Device for Accelerated DRAM Soft Error Detection
    Publication number: 20080266984
    Abstract: Aspects of the invention relate to a programmable heavy-ion sensing device for accelerated DRAM soft error detection. Design of a DRAM-based alpha particle sensing apparatus is preferred to be used as an accelerated on-chip SER test vehicle. The sensing apparatus is provided with programmable sensing margin, refresh rate, and supply voltage to achieve various degree of SER sensitivity. In addition, a dual-mode DRAM array is proposed so that at least a portion of the array can be used to monitor high-energy particle activities during soft-error detection (SED) mode.
    Type: Application
    Filed: June 6, 2008
    Publication date: October 30, 2008
    Applicant: International Business Machines Corporation
    Inventors: Howard H. Chen, John A. Fifield, Louis L. Hsu, Henry H.K. Tang
  • Using electrically programmable fuses to hide architecture, prevent reverse engineering, and make a device inoperable
    Patent number: 7442583
    Abstract: Techniques and systems whereby operation of and/or access to particular features of an electronic device may be controlled after the device has left the control of the manufacturer are provided. The operation and/or access may be provided based on values stored in non-volatile storage elements, such as electrically programmable fused (eFUSES).
    Type: Grant
    Filed: December 17, 2004
    Date of Patent: October 28, 2008
    Assignee: International Business Machines Corporation
    Inventors: Anthony R. Bonaccio, Karl R. Erickson, John A. Fifield, Chandrasekharan Kothandaraman, Phil C. Paone, William R. Tonti
  • Voltage Detection Circuit In An Integrated Circuit And Method Of Generating A Trigger Flag Signal
    Publication number: 20080169844
    Abstract: An integrated circuit that includes at least one tunneling device voltage detection circuit for generating a trigger flag signal. The tunneling device voltage detection circuit includes first and second voltage dividers receiving a supply voltage and having corresponding respective first and second internal node output voltages. The first and second voltage dividers are configured so the first output voltage is linear relative to the supply voltage and so that the second output voltage is nonlinear relative to the supply voltage. As the supply voltage ramps up, the profiles of the first and second output voltage cross at a particular voltage. An operational amplifier circuit senses when the first and second output voltages become equal and, in response thereto, outputs a trigger signal that indicates that the supply voltage has reached a certain level.
    Type: Application
    Filed: January 15, 2007
    Publication date: July 17, 2008
    Applicant: International Business Machines Corporation
    Inventors: Wagdi W. Abadeer, Jeffrey S. Brown, Albert M. Chu, John A. Fifield
  • STRUCTURE FOR A CURRENT CONTROL MECHANISM FOR DYNAMIC LOGIC KEEPER CIRCUITS
    Publication number: 20080169839
    Abstract: A design structure for an integrated circuit that includes a gate control voltage generator that supplies a current control gate voltage to a plurality of current control devices of a corresponding plurality of dynamic logic circuits each having a keeper circuit. The gate control voltage generator provides, via current control gate voltage, global control of the amount of keeper current flowing through the keeper circuits so as to enhance the performance of the dynamic logic circuits.
    Type: Application
    Filed: September 6, 2007
    Publication date: July 17, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Wagdi W. Abadeer, George M. Braceras, Albert M. Chu, John A. Fifield, Harold Pilo, Daryl M. Seitzer
  • Voltage Reference Circuit For Low Voltage Applications In An Integrated Circuit
    Publication number: 20080169869
    Abstract: An integrated circuit that includes at least one tunneling device voltage reference circuit for use in low voltage applications is disclosed. The tunneling device voltage reference circuit includes a pair of voltage dividing device stacks, one having a linear voltage output and the other having a non-linear voltage output. A feedback circuit supplies a regulated voltage to each of the voltage dividing stacks so that the output voltages of the two device stacks equalize. Once the feedback circuit has locked, any one of the device stack output voltages and the regulated voltage may be used as a voltage reference.
    Type: Application
    Filed: January 15, 2007
    Publication date: July 17, 2008
    Applicant: International Business Machines Corporation
    Inventors: Wagdi W. Abadeer, John A. Fifield
  • Current Control Mechanism For Dynamic Logic Keeper Circuits In An Integrated Circuit And Method Of Regulating Same
    Publication number: 20080169837
    Abstract: An integrated circuit that includes a gate control voltage generator that supplies a current control gate voltage to a plurality of current control devices of a corresponding plurality of dynamic logic circuits each having a keeper circuit. The gate control voltage generator provides, via current control gate voltage, global control of the amount of keeper current flowing through the keeper circuits so as to enhance the performance of the dynamic logic circuits.
    Type: Application
    Filed: January 15, 2007
    Publication date: July 17, 2008
    Applicant: International Business Machines Corporation
    Inventors: Wagdi W. Abadeer, George M. Braceras, Albert M. Chu, John A. Fifield, Harold Pilo, Daryl M. Seitzer
  • Programmable Locking Mechanism For Secure Applications In An Integrated Circuit
    Publication number: 20080155151
    Abstract: A programmable locking mechanism for use in an integrated circuit is disclosed. In particular, the programmable locking mechanism may include an access code storage circuit for storing a security access code and a code input register whose outputs feed a comparator circuit that generates a locking signal. The state of the locking signal depends on whether the contents of the access code storage circuit and the code input register match. Additionally, a blocking circuit is provided that interrupts a programming input to the access code storage circuit and, thus, allows or denies access via the programming input to the access code storage circuit depending on the state of the locking signal. Additionally, the locking signal is distributed to sensitive logic circuits within the integrated circuit for preventing and/or allowing (depending on state) access thereto.
    Type: Application
    Filed: December 22, 2006
    Publication date: June 26, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John A. Fifield, Steven F. Oakland, Michael R. Ouellette
  • Voltage Pump Circuit with an Oxide Stress Control Mechanism for use in High-Voltage Applications in an Integrated Circuit
    Publication number: 20080150617
    Abstract: A voltage pump circuit that has an oxide stress control mechanism is disclosed. In particular, the oxide stress control mechanism of the voltage pump circuit ensures a safe transistor gate-to-source voltage in high-voltage applications in an integrated circuit. In particular, the down level of the gate voltage of the output transistor may be conditionally limited. For example, an offset in the down level of the gate voltage is created by conditionally developing an offset voltage in the lower rail voltage of the gate driver. The offset voltage is created by directing a predetermined current through a resistance. The current is conditional such that the current is about zero when the power supply voltage is less than or equal to a predetermined level, and the current is greater than zero when the power supply voltage is greater than a predetermined level.
    Type: Application
    Filed: December 21, 2006
    Publication date: June 26, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: John A. Fifield
  • USING ELECTRICALLY PROGRAMMABLE FUSES TO HIDE ARCHITECTURE, PREVENT REVERSE ENGINEERING, AND MAKE A DEVICE INOPERABLE
    Publication number: 20080143373
    Abstract: Techniques and systems whereby operation of and/or access to particular features of an electronic device may be controlled after the device has left the control of the manufacturer are provided. The operation and/or access may be provided based on values stored in non-volatile storage elements, such as electrically programmable fused (eFUSES).
    Type: Application
    Filed: February 29, 2008
    Publication date: June 19, 2008
    Inventors: Anthony R. BONACCIO, Karl R. ERICKSON, John A. FIFIELD, Chandrasekharan KOTHANDARAMAN, Phil C. PAONE, William R. TONTI
  • Low Voltage Reference System
    Publication number: 20080129271
    Abstract: A voltage reference system that generates a stable reference voltage at varying supply voltages. The system receiving an input voltage and having a voltage pumping circuit that provides a power supply, regulated by a regulator circuit, to a bandgap reference circuit. The bandgap reference circuit generating a first output as a stable voltage value and delivering the first output to a clamping circuit which outputs the lesser of the stable voltage value and a fraction of the input voltage.
    Type: Application
    Filed: December 4, 2006
    Publication date: June 5, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: John A. Fifield
  • Non Volatile Memory RAD-hard (NVM-rh) System
    Publication number: 20080094896
    Abstract: The embodiments of the invention provide an apparatus, method, etc. for a non volatile memory RAD-hard (NVM-rh) system. More specifically, an IC permanent non-volatile storage element comprises an integrated semiconductor stable reference component, wherein the component is resistant to external radiation. The storage element further comprises e-fuse structures in the component and a sensing circuit coupled to the e-fuse structures. The sensing circuit is adapted to update an external device at a specified time interval to reduce incidence of soft errors and errors due to power failure. Moreover, the sensing circuit is adapted to cease updating the external device to program the e-fuse structures; and, continue updating the external device after programming the e-fuse structures.
    Type: Application
    Filed: October 19, 2006
    Publication date: April 24, 2008
    Inventors: Karl R. Erickson, John A. Fifield, Chandrasekara Kothandaraman, Phil C. Paone, William R. Tonti
  • Voltage controlled static random access memory
    Patent number: 7352609
    Abstract: A static random access memory (SRAM) (200, 400) comprising a plurality of SRAM cells (204), a plurality of wordlines (WL0-WLN) and a voltage regulator (240, 240?, 300, 516) for driving the wordlines with a wordline voltage signal (VWLP). The wordline voltage signal is determined so as to reduce the likelihood of occurrence of read-disturbances and other memory instabilities. In one embodiment, the wordline voltage signal is determined as a function of the metastability voltage (VMETA) of the SRAM cells and an adjusted most positive down level voltage (VAMPDL) that is a function of a predetermined voltage margin (VM) and a most positive down level voltage (VMPDL) that corresponds to the read-disturb voltage of the SRAM cells.
    Type: Grant
    Filed: August 15, 2005
    Date of Patent: April 1, 2008
    Assignee: International Business Machines Corporation
    Inventors: John A. Fifield, Harold Pilo
  • Voltage Controlled Static Random Access Memory
    Publication number: 20080062749
    Abstract: A static random access memory (SRAM) comprising a plurality of SRAM cells, a plurality of wordlines (WL0-WLN) and a voltage regulator for driving the wordlines with a wordline voltage signal (VWLP). The wordline voltage signal is determined so as to reduce the likelihood of occurrence of read-disturbances and other memory instabilities. In one embodiment, the wordline voltage signal is determined as a function of the metastability voltage (VMETA) of the SRAM cells and an adjusted most positive down level voltage (VAMPDL) that is a function of a predetermined voltage margin (VM) and a most positive down level voltage (VMPDL) that corresponds to the read-disturb voltage of the SRAM cells.
    Type: Application
    Filed: October 29, 2007
    Publication date: March 13, 2008
    Applicant: International Business Machines Corporation
    Inventors: John Fifield, Harold Pilo
  • Changing Chip Function Based on Fuse States
    Publication number: 20080061817
    Abstract: Systems, methods, and design structures whereby operation of and/or access to particular features of an electronic device may be controlled after the device has left the control of the manufacturer are provided. The operation and/or access may be provided based on values stored in non-volatile storage elements, such as electrically programmable fused (eFUSES).
    Type: Application
    Filed: October 30, 2007
    Publication date: March 13, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Karl Erickson, John Fifield, Chandrasekharan Kothandaraman, Phil Paone, William Tonti
  • Voltage Controlled Static Random Access Memory
    Publication number: 20080049534
    Abstract: A static random access memory (SRAM) comprising a plurality of SRAM cells, a plurality of wordlines(WL0-WLN) and a voltage regulator for driving the wordlines with a wordline voltage signal (VWLP). The wordline voltage signal is determined so as to reduce the likelihood of occurrence of read-disturbances and other memory instabilities. In one embodiment, the wordline voltage signal is determined as a function of the metastability voltage (VMETA) of the SRAM cells and an adjusted most positive down level voltage (VAMPDL) that is a function of a predetermined voltage margin (VM) and a most positive down level voltage (VMPDL) that corresponds to the read-disturb voltage of the SRAM cells.
    Type: Application
    Filed: October 25, 2007
    Publication date: February 28, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: John Fifield, Harold Pilo
  • ERROR CORRECTING LOGIC SYSTEM
    Publication number: 20080048711
    Abstract: The invention includes an error correcting logic system that allows critical circuits to be hardened with only one redundant unit and without loss of circuit performance. The system provides an interconnecting gate that suppresses a fault in one of at least two redundant dynamic logic gates that feed to the interconnecting gate. The system is applicable to dynamic or static logic systems. The system prevents propagation of a fault, and addresses not only soft errors, but noise-induced errors.
    Type: Application
    Filed: October 29, 2007
    Publication date: February 28, 2008
    Inventors: Kerry Bernstein, Philip Emma, John Fifield, Paul Kartschoke, William Klaasen, Norman Rohrer
  • Changing chip function based on fuse states
    Patent number: 7336095
    Abstract: Techniques and systems whereby operation of and/or access to particular features of an electronic device may be controlled after the device has left the control of the manufacturer are provided. The operation and/or access may be provided based on values stored in non-volatile storage elements, such as electrically programmable fuses (eFUSES).
    Type: Grant
    Filed: June 8, 2007
    Date of Patent: February 26, 2008
    Assignee: International Business Machines Corporation
    Inventors: Karl R. Erickson, John A. Fifield, Chandrasekharan Kothandaraman, Phil C. Paone, William R. Tonti
  • Error correcting logic system
    Patent number: 7336102
    Abstract: The invention includes an error correcting logic system that allows critical circuits to be hardened with only one redundant unit and without loss of circuit performance. The system provides an interconnecting gate that suppresses a fault in one of at least two redundant dynamic logic gates that feed to the interconnecting gate. The system is applicable to dynamic or static logic systems. The system prevents propagation of a fault, and addresses not only soft errors, but noise-induced errors.
    Type: Grant
    Filed: July 27, 2004
    Date of Patent: February 26, 2008
    Assignee: International Business Machines Corporation
    Inventors: Kerry Bernstein, Philip G. Emma, John A. Fifield, Paul D. Kartschoke, William A. Klaasen, Norman J. Rohrer