Abstract: An improved differential amplifier having circuitry to enhance the slew rate and to provide a means for nulling the offset voltage during fabrication of the amplifier as an integrated circuit. The differential amplifier comprises an input stage connected to a current mirror. A slew rate enhancement circuit injects current into selected points of the circuit when the input voltage exceeds a predetermined threshold. An offset trim circuit injects a selected amount of current into the current mirror to alter the current flow between the input stage and the current mirror, thereby reducing the offset voltage. The selected amount of current is dictated by diodes which may be permanently shorted at various stages during fabrication, both before and after the amplifier is enclosed in an IC package.

Abstract: A differential amplifier is provided having a pair of input transistors with first electrodes connected to a first voltage potential through a first current source, a second pair of electrodes providing a pair of input terminals for the differential amplifier, and a third pair of electrodes connected to a pair of terminals, the current produced by the first current source passing through the first and third electrodes of the pair of input transistors into the pair of terminals in a ratio related to the difference in voltage of input signals fed to the pair of input terminals and the degree of mismatch in the pair of input transistors. A selector network injects a compensation current substantially equal to the difference in the currents passing through the pair of input transistors when the voltages at the pair of inputs are equal, and which results from a mismatch in such pair of input transistors, into a selected one of the pair of terminals.

Abstract: A current control circuit which can be used to provide starting current during the build-up of an input voltage, and terminate the starting current when the input voltage has reached a predetermined level. The preferred embodiment employs three FETs and one bipolar transistor, located in a total of only two isolation pockets on an integrated circuit chip. The first FET, which is scaled to operate in its saturated region while the second FET is in its resistive region, transmits a current received from the second FET as an output starting current during the initial portion of the input voltage build-up. During this time the second FET holds the gate-source voltage of the first FET to a level less than its pinch-off voltage. The third FET has its gate and source terminals connected in parallel with the first FET, and its drain connected to the base of the bipolar transistor, which is also connected to shunt current away from the first FET when appropriately gated.