Patents by Inventor John A. Foley

John A. Foley has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8443262
    Abstract: In one embodiment an example apparatus includes a memory with an error detection system (EDS) that detects an error event in the memory. The error event involves at least one bit in the memory changing state erroneously. The apparatus also includes a scrub logic to scrub the memory and correct memory errors (e.g., bit errors). The apparatus also includes a scrub rate adaptive logic to selectively control a memory scrub frequency associated with the scrub logic where the control is based, at least in part, on a number of error events detected by the EDS during an interval of time. A memory scrub frequency is the rate that a memory is periodically scrubbed to remove errors.
    Type: Grant
    Filed: July 17, 2012
    Date of Patent: May 14, 2013
    Assignee: Cisco Technology, Inc.
    Inventor: John A. Foley
  • Publication number: 20120284575
    Abstract: In one embodiment an example apparatus includes a memory with an error detection system (EDS) that detects an error event in the memory. The error event involves at least one bit in the memory changing state erroneously. The apparatus also includes a scrub logic to scrub the memory and correct memory errors (e.g., bit errors). The apparatus also includes a scrub rate adaptive logic to selectively control a memory scrub frequency associated with the scrub logic where the control is based, at least in part, on a number of error events detected by the EDS during an interval of time. A memory scrub frequency is the rate that a memory is periodically scrubbed to remove errors.
    Type: Application
    Filed: July 17, 2012
    Publication date: November 8, 2012
    Applicant: CISCO TECHNOLOGY, INC.
    Inventor: John A. FOLEY
  • Patent number: 8255772
    Abstract: In one embodiment an example apparatus includes a memory with an error detection system (EDS) that detects an error event in the memory. The error event involves at least one bit in the memory changing state erroneously. The apparatus also includes a scrub logic to scrub the memory and correct memory errors (e.g., bit errors). The apparatus also includes a scrub rate adaptive logic to selectively control a memory scrub frequency associated with the scrub logic where the control is based, at least in part, on a number of error events detected by the EDS during an interval of time. A memory scrub frequency is the rate that a memory is periodically scrubbed to remove errors.
    Type: Grant
    Filed: June 18, 2008
    Date of Patent: August 28, 2012
    Assignee: CISCO TECHNOLOGY, Inc.
    Inventor: John A. Foley