Abstract: A serial optical link for transmission of payload data is utilised so as to permit transmission of information facility data unrelated to the payload data. A superframe is constructed at the transmission facility made up of a serial series of data frames. Each data frame consists of serially arranged words including a number of payload data words and a non-payload word. One non-payload word of the superframe has information facility data which provides a communication channel from the transmitting facility to the receiving facility for information unrelated to the communication of payload data. Another non-payload word has alarm and status facility data. The information facility data is stored in a FIFO buffer when received. If the FIFO buffer is within two words of being full, a full signal is incorporated in the next alarm and status facility data word which causes the receiving end to suspend sending information facility data words.

Abstract: A circuit for testing the integrity of transmission paths includes a first linear feedback shift register (LFSR) adapted to generate a periodic sequence of pseudo random test data for transmission on the transmission paths. A second LFSR synchronizes to the transmitted test data after being provided with a seed value corresponding to a transmitted data word. After synchronization, the second LFSR is set to a free running mode and independently generates a pseudo random sequence of patterns corresponding to the sequence generated by the first LFSR. A comparator compares the pseudo random data generated by the second LFSR with the pseudo random data received from the transmission paths. If a mismatch occurs a signal indicating an error condition is asserted.

Abstract: A method and apparatus are provided for receiving parallel digital data signals and an aligned frame pulse. The frame pulse occurs at a regular interval which is a multiple of the data clock period. A multiple clock sampling scheme includes sampling the frame pulse using a plurality of phase-shifted clock signals, selecting several clock signals which are centered on the frame pulse and therefore the data. Then, sampling the data using the selected clocks, taking a majority value of the multiple samples and aligning the sampled data with a locally generated frame pulse using an elastic store.

Abstract: A telephone ringing signal generator which sequentially produces a plurality of ringing signals each of a different frequency. Each of a plurality of tone ringers connected to the generator will ring only in response to it's particular frequency. A programmable oscillator generates the required frequencies under control of a time slot generator which defines the time slot during which each frequency is to be generated.

Abstract: A telephone ringing signal generator which produces a signal that can ring a plurality of connected ringers tuned to different frequencies. The ringing signal comprises sequentially varying frequencies and each ringer will ring in response to its particular frequency. A counter is used to define the duration of the ringing signal and enable each frequency sequentially. A variable sweep frequency oscillator is connected to the counter and generates a signal having a different frequency for each counter increment. A programmable filter shapes the signal into a sine wave which is amplified to ringing voltage levels by a ringing signal amplifier.

Abstract: A control point driver circuit for use in a telephone exchange for energizing and deenergizing a control element such as a control relay in response to set and reset input pulses. The control point driver circuit comprises a transformer having a centertapped primary forming set, reset, and common inputs for receiving the set and reset input pulses and a secondary coupled to a constant control voltage. The control point driver circuit also includes a comparator having a first input coupled to the transformer secondary, an output coupled to the control relay to be energized and de-energized and a second input coupled to the comparator output for receiving first and second reference voltages which are related in magnitude to the constant control voltage to maintain the comparator in the set state or reset state indefinitely until a reset or set input pulse is received.

Abstract: The disclosure relates to a control means for converting serially transmitted di-phase data bits into parallel data bits having corresponding discrete logic levels. The control means of the present invention is adapted for use in a di-phase pulse receiving system of the type which includes a positive peak detector for providing a first pulse upon detecting a positive di-phase signal portion and a negative peak detector for providing a second pulse upon detecting a negative di-phase signal portion.

Abstract: A register and sender module with an internal common control provided with common addressing, storage, and timing for up to four registers, up to two senders, and up to two tone control circuits in a module. Modular construction allows addition and replacement of the various circuits in the module on an as required basis with a minimum of rewiring. An internal bus couples all module circuits to the internal common control. Each register and sender in the module is accessible from every inlet to the module. Provision is made for single digit storage to the registers and senders and single digit read out from the sender.

Abstract: A TCMF and MF decoder with common decoder section and separate TCMF and MF control sections. The decoder is time shared between two or more registers served on a first-come, first-served basis with priority assigned to one in case of identical seizure time. Strapping options are provided to allow the two registers to be both TCMF registers, or both MF registers, or one of each.

Abstract: A dial pulse receiver having a clock pulse input to a counter and a first and second flip-flop. The outputs of the two flip-flops are coupled to an exclusive OR gate to reset the counter. The counter output and the two outputs of the second flip-flop are coupled to an output gate and latch configuration. The counter is set to enable the latches so only a legitimate dial pulse is recorded.

Abstract: A side of line detector with a single operational amplifier with adjustable output. The amplifier input is protected from positive and negative voltage spikes by diodes. Two transistors are coupled to the amplifier to set a comparator voltage reference which allows the rejection of leakage and noise. Test points are provided in the circuit to facilitate testing particular subcircuits and to allow the initial adjustment of the detector.

Abstract: A shift register is provided with two inputs and two outputs. One input is from a free running clock and a second input is provided for relay operate and release signals. The two outputs are coupled to a NAND gate to provide a longer relay operate than release time. The two outputs are coupled to a NOR gate for a longer relay release time than operate time. Either gate output is coupled to a relay driver to operate the relay.