Patents by Inventor John A Griesemer
John A Griesemer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10794948Abstract: An EM testing method includes forcing electrical current through EM monitor wiring arranged in close proximity to the perimeter of the TSV and measuring an electrical resistance drop across the EM monitor wiring. The method may further include determining if an electrical short exists between the EM monitor wiring and the TSV from the measured electrical resistance. The method may further include determining if an early electrical open or resistance increase exists within the EM monitoring wiring due to TSV induced proximity effect.Type: GrantFiled: November 7, 2017Date of Patent: October 6, 2020Assignee: International Business Machines CorporationInventors: Fen Chen, Mukta G. Farooq, John A. Griesemer, Chandrasekaran Kothandaraman, John M. Safran, Timothy D. Sullivan, Ping-Chuan Wang, Lijuan Zhang
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Patent number: 10677833Abstract: A structure, such as a wafer, semiconductor chip, integrated circuit, or the like, includes a through silicon via (TSV) and an electromigration (EM) monitor. The TSV) includes at least one perimeter sidewall. The EM monitor includes a first EM wire separated from the perimeter sidewall of the TSV by a dielectric.Type: GrantFiled: November 7, 2017Date of Patent: June 9, 2020Assignee: International Business Machines CorporationInventors: Fen Chen, Mukta G. Farooq, John A. Griesemer, Chandrasekaran Kothandaraman, John M. Safran, Timothy D. Sullivan, Ping-Chuan Wang, Lijuan Zhang
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Publication number: 20180074110Abstract: An EM testing method includes forcing electrical current through EM monitor wiring arranged in close proximity to the perimeter of the TSV and measuring an electrical resistance drop across the EM monitor wiring. The method may further include determining if an electrical short exists between the EM monitor wiring and the TSV from the measured electrical resistance. The method may further include determining if an early electrical open or resistance increase exists within the EM monitoring wiring due to TSV induced proximity effect.Type: ApplicationFiled: November 7, 2017Publication date: March 15, 2018Inventors: Fen Chen, Mukta G. Farooq, John A. Griesemer, Chandrasekaran Kothandaraman, John M. Safran, Timothy D. Sullivan, Ping-Chuan Wang, Lijuan Zhang
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Publication number: 20180074111Abstract: A structure, such as a wafer, semiconductor chip, integrated circuit, or the like, includes a through silicon via (TSV) and an electromigration (EM) monitor. The TSV) incldues at least one perimeter sidewall.Type: ApplicationFiled: November 7, 2017Publication date: March 15, 2018Inventors: Fen Chen, Mukta G. Farooq, John A. Griesemer, Chandrasekaran Kothandaraman, John M. Safran, Timothy D. Sullivan, Ping-Chuan Wang, Lijuan Zhang
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Patent number: 9891261Abstract: A structure, such as a wafer, chip, IC, design structure, etc., includes a through silicon via (TSV) and an electromigration (EM) monitor. The TSV extends completely through a semiconductor chip and the EM monitor includes a plurality of EM wires proximately arranged about the TSV perimeter. An EM testing method includes forcing electrical current through EM monitor wiring arranged in close proximity to the perimeter of the TSV, measuring an electrical resistance drop across the EM monitor wiring, determining if an electrical short exists between the EM monitor wiring and the TSV from the measured electrical resistance, and/or determining if an early electrical open or resistance increase exists within the EM monitoring wiring due to TSV induced proximity effect.Type: GrantFiled: June 30, 2014Date of Patent: February 13, 2018Assignee: International Business Machines CorporationInventors: Fen Chen, Mukta G. Farooq, John A. Griesemer, Chandrasekaran Kothandaraman, John M. Safran, Timothy D. Sullivan, Ping-Chuan Wang, Lijuan Zhang
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Patent number: 9404953Abstract: Embodiments of the present invention provide a variety of structures and method for detecting abnormalities in the back-end-of-line (BEOL) stack and BEOL structures located in close proximity to through-silicon vias (TSVs) in a 3D integrated chip. The detected abnormalities may include stress, strain, and damage that will affect metallization continuity, interfacial integrity within a metal level, proximity accuracy of the TSV placement, and interlevel dielectric integrity and metallization-to-TSV dielectric integrity. Additionally, these structures in conjunction with each other are capable of determining the range of influence of the TSV. That is, how close to the TSV that a BEOL line (or via) needs to be in order to be influenced by the TSV.Type: GrantFiled: October 31, 2013Date of Patent: August 2, 2016Assignee: International Business Machines CorporationInventors: Fen Chen, Mukta G. Farooq, John A. Griesemer, Chandrasekharan Kothandaraman, John Matthew Safran, Timothy Dooling Sullivan
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Publication number: 20150380326Abstract: A structure, such as a wafer, chip, IC, design structure, etc., includes a through silicon via (TSV) and an electromigration (EM) monitor. The TSV extends completely through a semiconductor chip and the EM monitor includes a plurality of EM wires proximately arranged about the TSV perimeter. An EM testing method includes forcing electrical current through EM monitor wiring arranged in close proximity to the perimeter of the TSV, measuring an electrical resistance drop across the EM monitor wiring, determining if an electrical short exists between the EM monitor wiring and the TSV from the measured electrical resistance, and/or determining if an early electrical open or resistance increase exists within the EM monitoring wiring due to TSV induced proximity effect.Type: ApplicationFiled: June 30, 2014Publication date: December 31, 2015Inventors: Fen Chen, Mukta G. Farooq, John A. Griesemer, Chandrasekaran Kothandaraman, John M. Safran, Timothy D. Sullivan, Ping-Chuan Wang, Lijuan Zhang
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Patent number: 9059167Abstract: The present invention relates to bonded semiconductor integrated circuits, more specifically to a structure to protect against crack propagation into any layer of such integrated circuits. Embodiments of the present invention may include a first semiconductor substrate having a first layer bonded to second layer of a substantially thinner second semiconductor substrate by a bonding layer. The first layer may contain a crack stop. The crack stop may be in contact with a circumferential wall, made up of posts, that extends through the bonding layer, the second layer, and the second substrate.Type: GrantFiled: July 31, 2014Date of Patent: June 16, 2015Assignee: International Business Machines CorporationInventors: Mukta G. Farooq, John A. Griesemer, William F. Landers, Ian D. Melville, Thomas M. Shaw, Huilong Zhu
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Patent number: 9040418Abstract: Method of forming a capture pad on a semiconductor substrate. The method includes providing a semiconductor substrate having an active side and an inactive side and having a plurality of unfilled TSVs extending between the active side and the inactive side; filling the TSVs with a metal; defining capture pad areas on at least one of the active side and the inactive side adjacent to the TSVs, the defined capture pad areas comprising insulator islands and open areas; filling the open areas with the same metal to form a capture pad in direct contact with each of the TSVs, each of the capture pads having an all metal portion that follows an outline of each of the TSVs.Type: GrantFiled: November 10, 2013Date of Patent: May 26, 2015Assignee: International Business Machines CorporationInventors: Mukta G. Farooq, John A. Griesemer, Gary Lafontant, Kevin S. Petrarca, Richard P. Volant
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Publication number: 20150115982Abstract: Embodiments of the present invention provide a variety of structures and method for detecting abnormalities in the back-end-of-line (BEOL) stack and BEOL structures located in close proximity to through-silicon vias (TSVs) in a 3D integrated chip. The detected abnormalities may include stress, strain, and damage that will affect metallization continuity, interfacial integrity within a metal level, proximity accuracy of the TSV placement, and interlevel dielectric integrity and metallization-to-TSV dielectric integrity. Additionally, these structures in conjunction with each other are capable of determining the range of influence of the TSV. That is, how close to the TSV that a BEOL line (or via) needs to be in order to be influenced by the TSV.Type: ApplicationFiled: October 31, 2013Publication date: April 30, 2015Applicant: International Business Machines CorporationInventors: Fen Chen, Mukta G. Farooq, John A. Griesemer, Chandrasekharan Kothandaraman, John Matthew Safran, Timothy Dooling Sullivan
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Publication number: 20140339703Abstract: A structure to prevent propagation of a crack into the active region of a 3D integrated circuit, such as a crack initiated by a flaw at the periphery of a thinned substrate layer or a bonding layer, and methods of forming the same is disclosed.Type: ApplicationFiled: July 31, 2014Publication date: November 20, 2014Inventors: Mukta G. Farooq, John A. Griesemer, William F. Landers, Ian D. Melville, Thomas M. Shaw, Huilong Zhu
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Patent number: 8859390Abstract: A structure to prevent propagation of a crack into the active region of a 3D integrated circuit, such as a crack initiated by a flaw at the periphery of a thinned substrate layer or a bonding layer, and methods of forming the same is disclosed.Type: GrantFiled: February 5, 2010Date of Patent: October 14, 2014Assignee: International Business Machines CorporationInventors: Mukta G Farooq, John A Griesemer, William F Landers, Ian D Melville, Thomas M Shaw, Huilong Zhu
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Patent number: 8772949Abstract: Method of forming a capture pad on a semiconductor substrate. The method includes providing a semiconductor substrate having an active side and an inactive side and having a plurality of unfilled TSVs extending between the active side and the inactive side; filling the TSVs with a metal such that the metal is recessed with respect to at least one of the active side and the inactive side and does not entirely fill the TSVs; defining capture pad areas on the at least one of the active side and inactive side adjacent to the recessed TSVs; filling the capture pad areas and recessed TSVs with the same metal to form a capture pad in direct contact with each of the TSVs, each of the capture pads having an all metal portion that follows an outline of each of the TSVs. Also disclosed is a semiconductor substrate having a capture pad.Type: GrantFiled: November 7, 2012Date of Patent: July 8, 2014Assignee: International Business Machines CorporationInventors: Mukta G. Farooq, John A. Griesemer, Gary Lafontant, Kevin S. Petrarca, Richard P. Volant
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Publication number: 20140127904Abstract: Method of forming a capture pad on a semiconductor substrate. The method includes providing a semiconductor substrate having an active side and an inactive side and having a plurality of unfilled TSVs extending between the active side and the inactive side; filling the TSVs with a metal; defining capture pad areas on at least one of the active side and the inactive side adjacent to the TSVs, the defined capture pad areas comprising insulator islands and open areas; filling the open areas with the same metal to form a capture pad in direct contact with each of the TSVs, each of the capture pads having an all metal portion that follows an outline of each of the TSVs.Type: ApplicationFiled: November 10, 2013Publication date: May 8, 2014Applicant: International Business Machines CorporationInventors: Mukta G. Farooq, John A. Griesemer, Gary Lafontant, Kevin S. Petrarca, Richard P. Volant
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Publication number: 20140124946Abstract: Method of forming a capture pad on a semiconductor substrate. The method includes providing a semiconductor substrate having an active side and an inactive side and having a plurality of unfilled TSVs extending between the active side and the inactive side; filling the TSVs with a metal such that the metal is recessed with respect to at least one of the active side and the inactive side and does not entirely fill the TSVs; defining capture pad areas on the at least one of the active side and inactive side adjacent to the recessed TSVs; filling the capture pad areas and recessed TSVs with the same metal to form a capture pad in direct contact with each of the TSVs, each of the capture pads having an all metal portion that follows an outline of each of the TSVs. Also disclosed is a semiconductor substrate having a capture pad.Type: ApplicationFiled: November 7, 2012Publication date: May 8, 2014Applicant: International Business Machines CorporationInventors: Mukta G. Farooq, John A. Griesemer, Gary Lafontant, Kevin S. Petrarca, Richard P. Volant
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Patent number: 8386977Abstract: A tool that allows three dimensional chip circuit designs to be checked subsequent to 3D design layer mirroring. The 3D chip design is converted to a corresponding 2D chip design by mirroring one or more design layers from the mirrored side of a 3D design and merging those design layers with unmirrored design layers from the unmirrored side of a 3D design. The converted circuit design can be processed by standard verification checks. The tool may also receive design layers corresponding to an integrated circuit that will pass through multiple semiconductor chips. Each design cell is examined to determine if it corresponds to a mirrored or unmirrored side of its respective semiconductor chip. If the respective design cell corresponds to the mirrored side, the design cell is mirrored. All mirrored cells are then merged with the unmirrored design cells in the correct order. The merged design is processed by standard verification checks.Type: GrantFiled: May 23, 2011Date of Patent: February 26, 2013Assignee: International Business Machines CorporationInventors: Mukta G. Farooq, John A. Griesemer, William Francis Landers, Kevin S. Petrarca, Richard Paul Volant
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Publication number: 20120304138Abstract: A tool that allows three dimensional chip circuit designs to be checked subsequent to 3D design layer mirroring. The 3D chip design is converted to a corresponding 2D chip design by mirroring one or more design layers from the mirrored side of a 3D design and merging those design layers with unmirrored design layers from the unmirrored side of a 3D design. The converted circuit design can be processed by standard verification checks. The tool may also receive design layers corresponding to an integrated circuit that will pass through multiple semiconductor chips. Each design cell is examined to determine if it corresponds to a mirrored or unmirrored side of its respective semiconductor chip. If the respective design cell corresponds to the mirrored side, the design cell is mirrored. All mirrored cells are then merged with the unmirrored design cells in the correct order. The merged design is processed by standard verification checks.Type: ApplicationFiled: May 23, 2011Publication date: November 29, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mukta G. Farooq, John A. Griesemer, William Francis Landers, Kevin S. Petrarca, Richard Paul Volant
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Patent number: 8288270Abstract: The embodiments provide a method for reducing electromigration in a circuit containing a through-silicon via (TSV) and the resulting novel structure for the TSV. A TSV is formed through a semiconductor substrate. A first end of the TSV connects to a first metallization layer on a device side of the semiconductor substrate. A second end of the TSV connects to a second metallization layer on a grind side of the semiconductor substrate. A first flat edge is created on the first end of the TSV at the intersection of the first end of the TSV and the first metallization layer. A second flat edge is created on the second end of the TSV at the intersection of the second end of the TSV and the second metallization layer. On top of the first end a metal contact grid is placed, having less than eighty percent metal coverage.Type: GrantFiled: February 15, 2012Date of Patent: October 16, 2012Assignee: International Business Machines CorporationInventors: Mukta G Farooq, John A Griesemer, Gary LaFontant, William Francis Landers, Timothy Dooling Sullivan
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Publication number: 20120199975Abstract: The embodiments provide a method for reducing electromigration in a circuit containing a through-silicon via (TSV) and the resulting novel structure for the TSV. A TSV is formed through a semiconductor substrate. A first end of the TSV connects to a first metallization layer on a device side of the semiconductor substrate. A second end of the TSV connects to a second metallization layer on a grind side of the semiconductor substrate. A first flat edge is created on the first end of the TSV at the intersection of the first end of the TSV and the first metallization layer. A second flat edge is created on the second end of the TSV at the intersection of the second end of the TSV and the second metallization layer. On top of the first end a metal contact grid is placed, having less than eighty percent metal coverage.Type: ApplicationFiled: February 9, 2011Publication date: August 9, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mukta G. Farooq, John A. Griesemer, Gary LaFontant, William Francis Landers, Timothy Dooling Sullivan
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Publication number: 20120199983Abstract: The embodiments provide a method for reducing electromigration in a circuit containing a through-silicon via (TSV) and the resulting novel structure for the TSV. A TSV is formed through a semiconductor substrate. A first end of the TSV connects to a first metallization layer on a device side of the semiconductor substrate. A second end of the TSV connects to a second metallization layer on a grind side of the semiconductor substrate. A first flat edge is created on the first end of the TSV at the intersection of the first end of the TSV and the first metallization layer. A second flat edge is created on the second end of the TSV at the intersection of the second end of the TSV and the second metallization layer. On top of the first end a metal contact grid is placed, having less than eighty percent metal coverage.Type: ApplicationFiled: February 15, 2012Publication date: August 9, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mukta G. Farooq, John A. Griesemer, Gary LaFontant, William Francis Landers, Timothy Dooling Sullivan