Patents by Inventor John A. Hughes

John A. Hughes has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250246442
    Abstract: A signal transmission or processing assembly having a coaxial through-via within a substrate is provided. The substrate may be formed from a material that is a glass-like with an amorphous non-crystalline structure that enables the assembly to create or be created by a deep trepan or annular member that surrounds the center conductor. Methods of manufacture are employed or exploited to preserve the glass-like or other dielectric material structure of substrate to form the inner material or annular member that surrounds the center conductor or pair of center conductors.
    Type: Application
    Filed: January 31, 2024
    Publication date: July 31, 2025
    Applicant: BAE Systems Information and Electronic Systems Integration Inc.
    Inventors: Jeffrey M. Fitzgerald, Zachary Hileman, John A. Hughes
  • Patent number: 9502269
    Abstract: An apparatus for cooling electronic devices to be used in the vacuum of space is described. a window frame is provided as packaging for an electronic device having a substrate and a chip. The window frame includes an opening to allow a heat pipe to be in direct contact with a backside of the chip. The window frame is hermetically sealed to the backside of the chip. The window frame is also welded to a kovar ring located on the backside of the chip to provide a hermetic seal between the window frame and the substrate.
    Type: Grant
    Filed: April 1, 2015
    Date of Patent: November 22, 2016
    Assignee: BAE Systems Information and Electronic Systems Integration Inc.
    Inventors: Alan M. Berard, John A. Hughes, Keith K. Sturcken, Timothy Whalen
  • Publication number: 20140175675
    Abstract: A method for manufacturing an electronic multi-chip module that involves stacking at least six tested devices to form the module. These devices may be individually tested prior to assembling the electronic module. After individually testing the devices, the devices may be stacked one on top of the other to form an electronic multi-chip module having at least six stacked devices. Other embodiments may be described and claimed.
    Type: Application
    Filed: February 27, 2014
    Publication date: June 26, 2014
    Applicant: BAE Systems Information and Electronic Systems Integration Inc.
    Inventors: Keith K. Sturcken, John A. Hughes, Thomas E. Love, Sheila J. Konecke, Jeffrey Montag, Peter M. Wallace
  • Patent number: 8697457
    Abstract: A method for manufacturing an electronic multi-chip module that involves stacking at least six tested devices to form the module. These devices may be individually tested prior to assembling the electronic module. After individually testing the devices, the devices may be stacked one on top of the other to form an electronic multi-chip module having at least six stacked devices. Other embodiments may be described and claimed.
    Type: Grant
    Filed: June 21, 2012
    Date of Patent: April 15, 2014
    Assignee: BAE Systems Information and Electronic Systems Integration Inc.
    Inventors: Keith K. Sturcken, John A. Hughes, Thomas E. Love, Sheila J. Konecke, Jeffrey Montag, Peter M. Wallace
  • Publication number: 20130309815
    Abstract: An electronic device package includes a substrate and wire columns arranged in groups about a neutral stress point of the substrate. The height of the wire columns is substantially uniform for the plural groups of wire columns, and a length of at least one of the wire columns is greater than the uniform height. A method of fabricating an electronic device package having a column grid array includes applying two templates on wire columns of the column grid array and bending at least one wire column to increase its length while maintaining a uniform height for the column grid array. In another aspect, an electronic device package substrate includes wire columns having at least one non-uniformity in lengths of the columns, and the length of a wire column corresponds to a distance of that wire column from the neutral stress point of the substrate.
    Type: Application
    Filed: July 26, 2013
    Publication date: November 21, 2013
    Applicant: BAE Systems Information and Electronic Systems Intergration Inc.
    Inventors: John A. Hughes, Christy A. Hagerty, Santos Nazario-Camacho, Keith K. Sturcken
  • Patent number: 8586417
    Abstract: An electronic device package includes a substrate and wire columns arranged in groups about a neutral stress point of the substrate. The height of the wire columns is substantially uniform for the plural groups of wire columns, and a length of at least one of the wire columns is greater than the uniform height. A method of fabricating an electronic device package having a column grid array includes applying two templates on wire columns of the column grid array and bending at least one wire column to increase its length while maintaining a uniform height for the column grid array. In another aspect, an electronic device package substrate includes wire columns having at least one non-uniformity in lengths of the columns, and the length of a wire column corresponds to a distance of that wire column from the neutral stress point of the substrate.
    Type: Grant
    Filed: July 26, 2013
    Date of Patent: November 19, 2013
    Assignee: BAE Systems Information and Electronic Systems Integration Inc.
    Inventors: John A. Hughes, Christy A. Hagerty, Santos Nazario-Camacho, Keith K. Sturcken
  • Patent number: 8580075
    Abstract: A method and system of for introducing an active material to a chemical process in which a processing element including a passive component and an active element is installed within the system and exposed to a chemical process performed within the system. As the chemical process proceeds, the passive component erodes and thereby exposes the active component embedded therein. The introduction of the active component to the chemical process alters the chemical process.
    Type: Grant
    Filed: April 20, 2012
    Date of Patent: November 12, 2013
    Assignee: Tokyo Electron Limited
    Inventors: John A. Hughes, Sandra Hyland, Ralph Kim
  • Patent number: 8519527
    Abstract: An electronic device package includes a substrate and wire columns arranged in groups about a neutral stress point of the substrate. The height of the wire columns is substantially uniform for the plural groups of wire columns, and a length of at least one of the wire columns is greater than the uniform height. A method of fabricating an electronic device package having a column grid array includes applying two templates on wire columns of the column grid array and bending at least one wire column to increase its length while maintaining a uniform height for the column grid array. In another aspect, an electronic device package substrate includes wire columns having at least one non-uniformity in lengths of the columns, and the length of a wire column corresponds to a distance of that wire column from the neutral stress point of the substrate.
    Type: Grant
    Filed: September 29, 2010
    Date of Patent: August 27, 2013
    Assignee: BAE Systems Information and Electronic Systems Integration Inc.
    Inventors: John A. Hughes, Christy A. Hagerty, Santos Nazario-Camacho, Keith K. Sturcken
  • Patent number: 8338230
    Abstract: A system and method are provided in which a first chip in a stacked multi-chip module configuration is affixed via one or more adhesion layers to a first portion of a partitioned interposer unit. Planar partitions of the interposer are physically bonded via multiple solder “bumps,” which possess high tensile strength but low resistance to horizontal shear force or torque. A second chip is affixed via one or more adhesion layers to the second portion of the partitioned interposer. The chips may thus be separated by horizontally and oppositely shearing or twisting the first and second portions of the partitioned interposer away from one another.
    Type: Grant
    Filed: September 27, 2011
    Date of Patent: December 25, 2012
    Assignee: BAE Systems Information and Electronic Systems Integration Inc.
    Inventors: John A. Hughes, Thomas E. Love, Eugene Lemoine, David H. Lee, Christopher Ebel
  • Publication number: 20120015480
    Abstract: A system and method are provided in which a first chip in a stacked multi-chip module configuration is affixed via one or more adhesion layers to a first portion of a partitioned interposer unit. Planar partitions of the interposer are physically bonded via multiple solder “bumps,” which possess high tensile strength but low resistance to horizontal shear force or torque. A second chip is affixed via one or more adhesion layers to the second portion of the partitioned interposer. The chips may thus be separated by horizontally and oppositely shearing or twisting the first and second portions of the partitioned interposer away from one another.
    Type: Application
    Filed: September 27, 2011
    Publication date: January 19, 2012
    Applicant: BAE Systems Information and Electronic Systems Integration Inc.
    Inventors: John A. Hughes, Thomas E. Love, Eugene Lemoine, Christopher Ebel, David Lee
  • Patent number: 8067829
    Abstract: A system and method are provided in which a first chip in a stacked multi-chip module configuration is affixed via one or more adhesion layers to a first portion of a partitioned interposer unit. Planar partitions of the interposer are physically bonded via multiple solder “bumps,” which possess high tensile strength but low resistance to horizontal shear force or torque. A second chip is affixed via one or more adhesion layers to the second portion of the partitioned interposer. The chips may thus be separated by horizontally and oppositely shearing or twisting the first and second portions of the partitioned interposer away from one another.
    Type: Grant
    Filed: April 29, 2009
    Date of Patent: November 29, 2011
    Assignee: BAE Systems Information and Electronic Systems Integration Inc.
    Inventors: John A. Hughes, Thomas E. Love, Eugene Lemoine, David H. Lee, Christopher Ebel
  • Publication number: 20110074009
    Abstract: An electronic device package includes a substrate and wire columns arranged in groups about a neutral stress point of the substrate. The height of the wire columns is substantially uniform for the plural groups of wire columns, and a length of at least one of the wire columns is greater than the uniform height. A method of fabricating an electronic device package having a column grid array includes applying two templates on wire columns of the column grid array and bending at least one wire column to increase its length while maintaining a uniform height for the column grid array. In another aspect, an electronic device package substrate includes wire columns having at least one non-uniformity in lengths of the columns, and the length of a wire column corresponds to a distance of that wire column from the neutral stress point of the substrate.
    Type: Application
    Filed: September 29, 2010
    Publication date: March 31, 2011
    Applicant: BAE Systems Information & Electronic Systems Integration Inc.
    Inventors: John A. Hughes, Christy A. Hagerty, Santos Nazario-Camacho, Keith K. Sturcken
  • Publication number: 20100276794
    Abstract: A system and method are provided in which a first chip in a stacked multi-chip module configuration is affixed via one or more adhesion layers to a first portion of a partitioned interposer unit. Planar partitions of the interposer are physically bonded via multiple solder “bumps,” which possess high tensile strength but low resistance to horizontal shear force or torque. A second chip is affixed via one or more adhesion layers to the second portion of the partitioned interposer. The chips may thus be separated by horizontally and oppositely shearing or twisting the first and second portions of the partitioned interposer away from one another.
    Type: Application
    Filed: April 29, 2009
    Publication date: November 4, 2010
    Applicant: BAE SYSTEMS Information and Electronic Systems Integration Inc.
    Inventors: John A. Hughes, Thomas E. Love, Eugene Lemoine, Christopher Ebel, David H. Lee
  • Patent number: 6314689
    Abstract: A transparent planar storm shield has framed panels (1, 2, 12) with predetermined transparency and predetermined resistance to storm pressure and to storm-debris impact. Panels (3, 9, 10) of the framed panels are preferably shatter-proof plastic material that includes predetermined polycarbonate. Frames (4, 5, 6, 7, 13) of the framed panels have strengths in proportion to thicknesses for predetermined storm protection by predetermined areas of the storm shield. The storm shield is a cover of a predetermined portion of a building orifice which can include a door or a window. The predetermined resistance to storm pressure and to storm-debris impact of the panels is about an equivalent to a commercial grade of polycarbonate or an equivalent thereof that is twenty-five inches square with a thickness of one-eighth of an inch and being rectangular with less than twenty-five percent deviation from being square.
    Type: Grant
    Filed: July 17, 2000
    Date of Patent: November 13, 2001
    Inventor: John A. Hughes
  • Patent number: 3959825
    Abstract: A reversible four-in-hand necktie is herein disclosed, which has a first side bearing a first pattern. A second side, bearing a different pattern, is connected to the first side. The first and second sides are symmetric; and together form a pair of relatively wide end portions, which are connected by a narrow neck portion positioned between the end portions. The reversible four-in-hand necktie is used and worn as any other four-in-hand necktie, with the exception that either the first or second side is worn facing outward from the wearer.
    Type: Grant
    Filed: May 2, 1975
    Date of Patent: June 1, 1976
    Inventor: John A. Hughes