Abstract: A memory module according to one implementation includes a support substrate, plural memory devices mounted on the support substrate, and pins having a predetermined arrangement on the support substrate, the pins comprising signal pins connected to the memory devices, power pins, and ground pins. In the predetermined arrangement of pins, each signal pin uses a ground pin as a reference, and each power pin is adjacent a ground pin for reduced impedance between the power pin and ground pin. In some implementations, some of the signal pins are associated with redundant pins.

Abstract: A method for controlling application of an erasure mode of an error correction code (ECC) algorithm in a memory subsystem includes detecting errors in cache lines retrieved from the memory subsystem using the ECC algorithm. The method also analyzes the errors to detect a repeated bit pattern of data corruption within the cache lines, correlates the detected repeated bit pattern of data corruption to one of a plurality of domains of the memory subsystem, and applies the ECC algorithm to erase bits associated with the detected repeated bit pattern from cache lines retrieved from the correlated domain of the memory subsystem.

Abstract: A system utilizing an erasure mode in an error correction code algorithm is described that includes non-volatile memory storing a page deallocation table. A memory controller stores and retrieves data from a memory subsystem, and uses an error correction code algorithm to correct data corruption in retrieved data. An error analysis algorithm executed in a processor records instances of data corruption in the page deallocation tables and deallocates memory regions associated with multiple occurrences of data corruption at single bit locations. The error analysis algorithm further causes the memory controller to apply an erasure mode of the error correction code algorithm upon detection of a repeated pattern of data corruption across different addresses of the memory subsystem, and removes entries in the page deallocation table that correspond to data corruption addressed by application of the erasure mode.

Abstract: In one embodiment, a computer readable medium comprises code for recording occurrences of data corruption in data retrieved from a memory subsystem, code for determining whether bit locations within the memory subsystem are associated with multiple occurrences of data corruption, code for deallocating, in response to the code for determining, memory regions containing bit locations associated with multiple occurrences of data corruption, code for analyzing patterns of data corruption repeated across multiple addresses of the memory subsystem, and code for controlling application of an error correction code (ECC) algorithm by the memory subsystem to erase bits associated with a repeated bit pattern, detected by the code for analyzing, from data retrieved from the memory subsystem.

Abstract: A microcontroller is configured to interfaces with one or more dual in line memory modules (DIMMs) over an I2C bus and with a memory controller. The microcontroller efficiently retrieves configuration information from the DIMMs and provides it to the memory controller. During system power-up or reset, the memory configuration information, including power consumption parameters, is loaded by the microcontroller into the memory controller. The memory controller utilizes the power consumption parameters to control the rate at which built-in self test (BIST) operations are performed by the DIMMs, thereby conserving power.

Abstract: An improved asynchronous interface is provided between a custom device and a microcontroller, each capable of retrieving information from a memory device of a multiprocessor system. The custom device is preferably an application specific integrated circuit (ASIC) for controlling the memory device, and the memory device is preferably a dual in-line memory module (DIMM). The microcontroller interfaces with the DIMM over an I2C bus to obtain configuration and other information. The interface includes a protocol that efficiently utilizes data and control paths between the microcontroller and the memory controller to retrieve the configuration and other information from the DIMMs.